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PDF 83C196EA Data sheet ( Hoja de datos )
| Número de pieza | 83C196EA | |
| Descripción | CHMOS 16-BIT MICROCONTROLLER | |
| Fabricantes | Intel Corporation | |
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ADVANCE INFORMATION
83C196EA
CHMOS 16-BIT MICROCONTROLLER
Automotive
s 40 MHz operation
s Optional clock doubler
s 2 Mbytes of linear address space
s 1 Kbyte of register RAM
s 3 Kbytes of code RAM
s 8 Kbytes of ROM
s Register-to-register architecture
s Stack overflow/underflow monitor with
user-defined upper and lower stack
pointer boundary limits
s 2 peripheral interrupt handlers (PIH)
provide direct hardware handling of up
to 16 peripheral interrupts
s Peripheral transaction server (PTS) with
high-speed, microcoded interrupt
service routines
s Up to 83 I/O port pins
s 2 full-duplex serial ports with dedicated
baud-rate generators
s Enhanced synchronous serial unit
s 8 pulse-width modulator (PWM) outputs
with 8-bit resolution
s 16-bit watchdog timer
s Sixteen 10-bit A/D channels with auto-
scan mode and dedicated results
registers
s Serial debug unit provides read and
write access to code RAM with no CPU
overhead
s Chip-select unit (CSU)
s 3 chip-select pins
s Dynamic demultiplexed/multiplexed
address/data bus for each
chip-select
s Programmable wait states
(0, 1, 2, or 3) for each chip-select
s Programmable bus width
(8- or 16-bit) for each chip-select
s Programmable address range for each
chip-select
s Event processor array (EPA)
s 4 flexible 16-bit timer/counters
s 17 high-speed capture/compare
channels
s 8 output-only channels capture value of
any other timer upon compare, providing
easy conversion between angle and time
domains
s Programmable clock output signal
s 160-pin QFP package
s Complete system development support
s High-speed CHMOS technology
The 83C196EA is the first member of a new family of microcontrollers with features that are useful in
automotive applications, such as powertrain control. Two Mbytes of linear address space provide more space
for high-level language compilation. A demultiplexed address/data bus and three chip-select signals make it
easier to design low-cost memory solutions. The external bus can dynamically switch between multiplexed
and demultiplexed operation.
NOTE
This datasheet contains information on products being sampled or in the initial production
phase of development. The specifications are subject to change without notice. Verify
with your local Intel sales office that you have the latest datasheet before finalizing a
design.
COPYRIGHT © INTEL CORPORATION, 1997
March 1997
Order Number: 272788-002
1 page  
83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
1.0 PRODUCT OVERVIEW
Port 11
Port 10
Watchdog
Timer
Stack
Overflow
Module
A/D Pulse-width
Converter Modulators
SSIO0
SSIO1
EPORT Port 12
Peripheral Addr Bus (10)
Peripheral Data Bus (16)
Bus Control
A20:16
A15:0
AD15:0
Bus
Controller
Bus-Control
Interface Unit
Queue
Microcode
Engine
Source (16)
Register
Memory
ALU
RAM
1 Kbyte
Interface
Unit
Destination (16)
Chip-select
Unit
Peripheral
Interrupt
Handler
Peripheral
Transaction
Server
Interrupt
Controller
SIO0
Baud-rate
Generator
Port 2
SIO1
Baud-rate
Generator
Ports 7,8
EPA
17 Capture/
Compares
4 Timers
8 Output/
Simulcaptures
Port 9
Code/Data
RAM
Serial Debug
3 Kbytes
Unit
ROM
8 Kbytes
A3178-03
Figure 1. 83C196EA Block Diagram
The 83C196EA is highly integrated with an enhanced peripheral set. The serial debug unit (SDU) provides
system debug and development capabilities. The SDU can set a single hardware breakpoint and provides
read and write access to code RAM through a high-speed, dedicated serial link. A stack overflow/underflow
monitor assists in code development by causing an unmaskable interrupt if the stack pointer crosses a user-
defined boundary. The 16-channel A/D converter supports an auto-scan mode that operates with no CPU
ADVANCE INFORMATION
1
5 Page 
Name
AD15:0
ALE
ANGND
BHE#
BREQ#
83C196EA CHMOS 16-BIT MICROCONTROLLER — AUTOMOTIVE
Type
I/O
O
GND
O
O
Table 4. Signal Descriptions (Continued)
Description
Address/Data Lines
The function of these pins depend on the bus size and mode. When a bus
access is not occurring, these pins revert to their I/O port function.
16-bit Multiplexed Bus Mode:
AD15:0 drive address bits 0–15 during the first half of the bus cycle and drive or
receive data during the second half of the bus cycle.
8-bit Multiplexed Bus Mode:
AD15:8 drive address bits 8–15 during the entire bus cycle. AD7:0 drive
address bits 0–7 during the first half of the bus cycle and drive or receive data
during the second half of the bus cycle.
16-bit Demultiplexed Mode:
AD15:0 drive or receive data during the entire bus cycle.
8-bit Demultiplexed Mode:
AD7:0 drive or receive data during the entire bus cycle. AD15:8 drive the data
that is currently on the high byte of the internal bus.
Address Latch Enable
This active-high output signal is asserted only during external memory cycles.
ALE signals the start of an external bus cycle and indicates that valid address
information is available on the system address/data bus (A20:16 and AD15:0
for a multiplexed bus; A20:0 for a demultiplexed bus).
An external latch can use this signal to demultiplex address bits 0–15 from the
address/data bus in multiplexed mode.
ALE shares a package pin with P5.0.
Analog Ground
ANGND must be connected for A/D converter operation. ANGND and VSS
should be nominally at the same potential.
Byte High Enable†
During 16-bit bus cycles, this active-low output signal is asserted for word and
high-byte reads and writes to external memory. BHE# indicates that valid data
is being transferred over the upper half of the system data bus. Use BHE#, in
conjunction with AD0, to determine which memory byte is being transferred
over the system bus:
BHE# AD0 Byte(s) Accessed
0 0 both bytes
0 1 high byte only
1 0 low byte only
BHE# shares a package pin with P5.5 and WRH#.
† The chip configuration register 0 (CCR0) determines whether this pin func-
tions as BHE# or WRH#. CCR0.2 = 1 selects BHE#; CCR0.2 = 0 selects
WRH#.
Bus Request
This active-low output signal is asserted during a hold cycle when the bus
controller has a pending external memory cycle.
You must enable the bus-hold protocol before using this signal.
BREQ# shares a package pin with P5.4.
ADVANCE INFORMATION
7
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