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82C88 の電気的特性と機能

82C88のメーカーはIntersil Corporationです、この部品の機能は「CMOS Bus Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 82C88
部品説明 CMOS Bus Controller
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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82C88 Datasheet, 82C88 PDF,ピン配置, 機能
82C88
March 1997
CMOS Bus Controller
Features
Description
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 80186/80188 . . . . . . . . . . . . . . . . . . . . . . . . . .(6/8MHz)
- 8086/8088 . . . . . . . . . . . . . . . . . . . . . . . . . . . .(5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master
Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10µA (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . .1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
The Intersil 82C88 is a high performance CMOS Bus Con-
troller manufactured using a self-aligned silicon gate CMOS
process (Scaled SAJI IV). The 82C88 provides the control
and command timing signals for 80C86, 80C88, 8086, 8088,
8089, 80186, and 80188 based systems. The high output
drive capability of the 82C88 eliminates the need for addi-
tional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Ordering Information
PART NUMBER
CP82C88
CP82C88-10
IP82C88
CS82C88
IS82C88
CD82C88
ID82C88
MD82C88/B
8406901RA
MR82C88/B
84069012A
PACKAGE
20 Ld PDIP
20 Ld
PLCC
20 Ld
CERDIP
SMD#
20 Pad
CLCC
SMD#
TEMPERATURE
RANGE
0oC to +70oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG.
NO.
E20.3
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
20 LEAD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LEAD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
18 S2
17 MCE/PDEN
16 DEN
MRDC 7
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-333
File Number 2979.1

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82C88 pdf, ピン配列
82C88
Pin Description (Continued)
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
AIOWC
12
O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine
cycle to give I/O devices an early indication of a write instruction. Its timing is the same as a read com-
mand signal. AIOWC is active LOW.
IOWC 11 O I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The
signal is active LOW.
IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This
signal is active LOW.
AMWC
8
O ADVANCED MEMORY WRITE COMMAND: The AMWC issues a memory write command earlier in the
machine cycle to give memory devices an early indication of a write instruction. Its timing is the same as
a read command signal. AMWC is active LOW.
MWTC
9
O MEMORY WRITE COMMAND: This command line instructs the memory to record the data present on
the data bus. This signal is active LOW.
MRDC 7 O MEMORY READ COMMAND: This command line instructs the memory to drive its data onto the data
bus. MRDC is active LOW.
INTA
14 O INTERRUPT ACKNOWLEDGE: This command line tells an interrupting device that its interrupt has been
acknowledged and that it should drive vectoring information onto the data bus. This signal is active LOW.
MCE/PDEN 17
O This is a dual function pin. MCE (IOB IS TIED LOW) Master Cascade Enable occurs during an interrupt
sequence and serves to read a Cascade Address from a master 82C59A Priority Interrupt Controller onto
the data bus. The MCE signal is active HIGH. PDEN (IOB IS TIED HIGH): Peripheral Data Enable enables
the data bus transceiver for the I/O bus that DEN performs for the system bus. PDEN is active LOW.
Functional Description
The command logic decodes the three 80C86, 8086, 80C88,
8088, 80186, 80188 or 8089 status lines (S0, S1, S2) to
determine what command is to be issued (see Table 1).
TABLE 1. COMMAND DECODE DEFINITION
S2 S1 S0 PROCESSOR STATE
82C88
COMMAND
0 0 0 Interrupt Acknowledge INTA
0 0 1 Read I/O Port
IORC
0 1 0 Write I/O Port
IOWC, AIOWC
0 1 1 Halt
None
1 0 0 Code Access
MRDC
1 0 1 Read Memory
MRDC
1 1 0 Write Memory
MWTC, AMWC
1 1 1 Passive
None
cessor, the 82C88 immediately activates the command lines
using PDEN and DT/R to control the I/O bus transceiver. The
I/O command lines should not be used to control the system
bus in this configuration because no arbitration is present.
This mode allows one 82C88 Bus Controller to handle two
external busses. No waiting is involved when the CPU wants
to gain access to the I/O bus. Normal memory access
requires a “Bus Ready” signal (AEN LOW) before it will pro-
ceed. It is advantageous to use the IOB mode if I/O or
peripherals dedicated to one processor exist in a multi-pro-
cessor system.
System Bus Mode
The 82C88 is in the System Bus mode if the IOB pin is
strapped LOW. In this mode, no command is issued until a
specified time period after the AEN line is activated (LOW).
This mode assumes bus arbitration logic will inform the bus
controller (on the AEN line) when the bus is free for use.
Both memory and I/O commands wait for bus arbitration.
This mode is used when only one bus exists. Here, both I/O
and memory are shared by more than one processor.
I/O Bus Mode
The 82C88 is in the I/O Bus mode if the IOB pin is strapped
HIGH. In the I/O Bus mode, all I/O command lines IORC,
IOWC, AIOWC, INTA) are always enabled (i.e., not depen-
dent on AEN). When an I/O command is initiated by the pro-
Command Outputs
The advanced write commands are made available to initiate
write procedures early in the machine cycle. This signal can
be used to prevent the processor from entering an unneces-
sary wait state.
4-335


3Pages


82C88 電子部品, 半導体
82C88
AC Electrical Specifications
VCC = 5.0V ± 10%;
TA
TA
TA
=
=
=
0oC to +70oC (C82C88);
-40oC to +85oC (I82C88);
-55oC to +125oC (M82C88)
8MHz
10MHz
SYMBOL
PARAMETER
MIN MAX MIN MAX
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period
125 - 100 -
(2) TCLCH CLK Low Time
55 - 50 -
(3) TCHCL CLK High Time
40 - 37 -
(4) TSVCH Status Active Setup Time
35 - 35 -
(5) TCHSV Status Inactive Hold Time
10 - 10 -
(6) TSHCL Status Inactive Setup Time
35 - 35 -
(7) TCLSH Status Active Hold Time
10 - 10 -
TIMING RESPONSES
(8) TCVNV Control Active Delay
5 45 5 45
(9) TCVNX Control Inactive Delay
10 45 10 45
(10) TCLLH ALE Active Delay (from CLK) - 20 - 20
(11) TCLMCH MCE Active Delay (from CLK)
-
25
-
23
(12) TSVLH ALE Active Delay (from Status)
-
20
-
20
(13) TSVMCH MCE Active Delay (from Status)
-
30
-
23
(14) TCHLL ALE Inactive Delay
4 18 4 18
(15) TCLML Command Active Delay
5 35 5 35
(16) TCLMH Command Inactive Delay
5 35 5 35
(17) TCHDTL Direction Control Active Delay
-
50
-
50
(18) TCHDTH Direction Control Inactive Delay
-
30
-
30
(19) TAELCH Command Enable Time (Note 1) - 40 - 40
(20) TAEHCZ Command Disable Time
(Note 2)
- 40 - 40
(21) TAELCV Enable Delay Time
110 250 110 250
(22) TAEVNV AEN to DEN
- 25 - 25
(23) TCEVNV CEN to DEN, PDEN
- 25 - 25
(24) TCELRH CEN to Command
- TCLML - TCLML
+10
(25) TLHLL ALE High Time
TCLCH - - TCLCH - -
10 10
NOTES:
1. TAELCH measurement is between 1.5V and 2.5V.
2. TAEHCZ measured at 0.5V change in VOUT.
12MHz
MIN MAX
83 -
34 -
34 -
35 -
5-
35 -
5-
5 45
10 35
- 20
- 23
- 20
- 23
4 18
5 35
5 35
- 50
- 30
- 40
- 40
110 250
- 25
- 25
- TCLML
TCLCH -
10
n
TEST
UNITS CONDITIONS
ns
ns
ns
ns
ns
ns
ns
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 1
ns 2
ns 2
ns 1
ns 1
ns 3
ns 4
ns 2
ns 1
ns 1
ns 2
ns 1
AC Testing Input, Output Waveform
INPUT
VIH +0.4V
1.5V
VIL -0.4V
OUTPUT
VOH
1.5V
VOL
A.C. Testing: All input signals (other than CLK) must switch
between VIL -0.4V and VIH +0.4. CLK must switch between 0.4V
and VCC -0.4V. Input rise and fall times are driven at 1ns/V.
A.C. Test Circuit
V1
OUTPUT FROM
DEVICE
UNDER TEST
NOTE:
INCLUDES STRAY AND JIG CAPACITANCE
R1
TEST
POINT
C1 (SEE NOTE)
TABLE 2. TEST CONDITION DEFINITION TABLE
TEST CONDITION
1
2
3
4
V1
2.13V
2.29V
1.5V
1.5V
R1
220
91
187
187
C1
80pF
300pF
300pF
50pF
4-338

6 Page



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