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82C85 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 82C85
部品説明 CMOS Static Clock Controller/Generator
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 



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82C85 Datasheet, 82C85 PDF,ピン配置, 機能
82C85
March 1997
CMOS Static Clock Controller/Generator
Features
Description
• Generates the System Clock For CMOS or NMOS
Microprocessors and Peripherals
• Complete Control Over System Operation for Very
Low System Power
- Stop-Oscillator
- Low Frequency
- Stop-Clock
- Full Speed Operation
• DC to 25MHz Operation (DC to 8MHz System Clock)
• Generates 50% and 33% Duty Cycle Clocks
(Synchronized)
• Uses a Parallel Mode Crystal Circuit or External
Frequency Source
• TTL Compatible Inputs/Outputs
• 24 Lead Slimline Dual-In-Line or 28 Pad Square LCC
Package Options
• Single 5V Power Supply
• Operating Temperature Range
- C82C85 . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C85 . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C85 . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Ordering Information
PART NUMBER
CS82C85
IS82C85
CD82C85
ID82C85
MD82C85/B
MR82C85/B
PACKAGE
28 Ld PLCC
24 Ld CERDIP
28 Pad CLCC
TEMP. RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
PKG. NO.
N28.45
N28.45
F24.3
F24.3
F24.3
J28.A
The Intersil 82C85 Static CMOS Clock Controller/Genera-
tor provides complete control of static CMOS system oper-
ating modes and supports full speed, slow, stop-clock and
stop-oscillator operation. While directly compatible with the
Intersil 80C86 and 80C88 16-bit Static CMOS Microproces-
sor Family, the 82C85 can also be used for general system
clock control.
For static system designs, separate signals are provided on
the 82C85 for stop (S0, S1, S2/STOP) and start (START)
control of the crystal oscillator and system clocks. A single
control line (SLO/FST) determines 82C85 fast (crystal/EFI
frequency divided by 3) or slow (crystal/EFI frequency
divided by 768) mode operation. Automatic maximum
mode 80C86 and 80C88 software HALT instruction decode
logic in the 82C85 enables software-based clock control.
Restart logic insures valid clock start-up and complete syn-
chronization of system clocks.
The 82C85 is manufactured using the Intersil advanced
Scaled SAJI IV CMOS process. In addition to clock control
circuitry, the 82C85 also contains a crystal controlled
oscillator (up to 25MHz), clock generation logic, complete
“Ready” synchronization and reset logic. This permits the
designer to tailor the system power-performance product to
provide optimum performance at low power levels.
Pinouts
24 LEAD CERDIP
TOP VIEW
CSYNC 1
PCLK 2
AEN1 3
RDY1 4
READY 5
RDY2 6
AEN2 7
CLK 8
GND 9
CLK50 10
START 11
SLO/FST 12
24 VCC
23 X1
22 X2
21 ASYNC
20 EFI
19 F/C
18 OSC
17 RES
16 RESET
15 S2/STOP
14 S1
13 S0
28 LEAD PLCC, CLCC
TOP VIEW
4 3 2 1 28 27 26
RDY1 5
25 NC
READY 6
24 ASYNC
RDY2 7
23 EFI
AEN2 8
22 F/C
CLK 9
21 OSC
GND 10
20 RES
NC 11
19 RESET
12 13 14 15 16 17 18
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-297
File Number 2976.1

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