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82C83 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 82C83
部品説明 CMOS Octal Latching Inverting Bus Driver
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 



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82C83 Datasheet, 82C83 PDF,ピン配置, 機能
82C83H
March 1997
CMOS Octal Latching Inverting Bus Driver
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC
- I82C83H . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
- M82C83H . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8-
bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
PART NO.
CP82C83H
IP82C83H
CS82C83H
IS82C83H
CD82C83H
ID82C83H
MD82C83H/B
8406702RA
MR82C83H/B
84067022A
PACKAGE
20 Ld PDIP
20 Ld PLCC
20 Ld CERDIP
SMD#
20 Pad CLCC
SMD#
TEMP RANGE
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-40oC to +85oC
0oC to +70oC
-55oC to +125oC
-55oC to +125oC
-55oC to +125oC
PKG. NO
E20.3
E20.3
N20.35
N20.35
F20.3
F20.3
F20.3
F20.3
J20.A
J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
82C83H (PLCC, CLCC)
TOP VIEW
DI0 1
DI1 2
DI2 3
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
OE 9
GND 10
20 VCC
19 DO0
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
13 DO6
12 DO7
11 STB
3 2 1 20 19
DI3 4
DI4 5
DI5 6
DI6 7
DI7 8
18 DO1
17 DO2
16 DO3
15 DO4
14 DO5
9 10 11 12 13
STB
X
H
H
H = Logic One
L = Logic Zero
X = Don‘t Care
TRUTH TABLE
OE DI DO
H X HI-Z
L LH
LHL
LX
HI-Z = High Impedance
= Negative Transition
= Latched to Value of Last
Data
PIN
DI0 - DI7
DO0 - DO7
STB
OE
PIN NAMES
DESCRIPTION
Data Input Pins
Data Output Pins
Active High Strobe
Active Low Output Enable
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
4-281
File Number 2971.1

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