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82C54 の電気的特性と機能

82C54のメーカーはIntel Corporationです、この部品の機能は「CHMOS PROGRAMMABLE INTERVAL TIMER」です。


製品の詳細 ( Datasheet PDF )

部品番号 82C54
部品説明 CHMOS PROGRAMMABLE INTERVAL TIMER
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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82C54 Datasheet, 82C54 PDF,ピン配置, 機能
82C54
CHMOS PROGRAMMABLE INTERVAL TIMER
Y Compatible with all Intel and most
other microprocessors
Y High Speed ‘‘Zero Wait State’’
Operation with 8 MHz 8086 88 and
80186 188
Y Handles Inputs from DC
10 MHz for 82C54-2
Y Available in EXPRESS
Standard Temperature Range
Extended Temperature Range
Y Three independent 16-bit counters
Y Low Power CHMOS
ICC e 10 mA 8 MHz Count
frequency
Y Completely TTL Compatible
Y Six Programmable Counter Modes
Y Binary or BCD counting
Y Status Read Back Command
Y Available in 24-Pin DIP and 28-Pin PLCC
The Intel 82C54 is a high-performance CHMOS version of the industry standard 8254 counter timer which is
designed to solve the timing control problems common in microcomputer system design It provides three
independent 16-bit counters each capable of handling clock inputs up to 10 MHz All modes are software
programmable The 82C54 is pin compatible with the HMOS 8254 and is a superset of the 8253
Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator
programmable one-shot and in many other applications
The 82C54 is fabricated on Intel’s advanced CHMOS III technology which provides low power consumption
with performance equal to or greater than the equivalent HMOS product The 82C54 is available in 24-pin DIP
and 28-pin plastic leaded chip carrier (PLCC) packages
231244 – 3
PLASTIC LEADED CHIP CARRIER
231244 –1
Figure 1 82C54 Block Diagram
October 1994
231244 – 2
Diagrams are for pin reference only
Package sizes are not to scale
Figure 2 82C54 Pinout
Order Number 231244-006

1 Page





82C54 pdf, ピン配列
82C54
Block Diagram
DATA BUS BUFFER
This 3-state bi-directional 8-bit buffer is used to in-
terface the 82C54 to the system bus (see Figure 3)
CONTROL WORD REGISTER
The Control Word Register (see Figure 4) is selected
by the Read Write Logic when A1 A0 e 11 If the
CPU then does a write operation to the 82C54 the
data is stored in the Control Word Register and is
interpreted as a Control Word used to define the
operation of the Counters
The Control Word Register can only be written to
status information is available with the Read-Back
Command
231244 –4
Figure 3 Block Diagram Showing Data Bus
Buffer and Read Write Logic Functions
READ WRITE LOGIC
The Read Write Logic accepts inputs from the sys-
tem bus and generates control signals for the other
functional blocks of the 82C54 A1 and A0 select
one of the three counters or the Control Word Regis-
ter to be read from written into A ‘‘low’’ on the RD
input tells the 82C54 that the CPU is reading one of
the counters A ‘‘low’’ on the WR input tells the
82C54 that the CPU is writing either a Control Word
or an initial count Both RD and WR are qualified by
CS RD and WR are ignored unless the 82C54 has
been selected by holding CS low
The WR and CLK signals should be synchronous
This is accomplished by using a CLK input signal to
the 82C54 counters which is a derivative of the sys-
tem clock source Another technique is to externally
synchronize the WR and CLK input signals This is
done by gating WR with CLK
231244 – 5
Figure 4 Block Diagram Showing Control Word
Register and Counter Functions
COUNTER 0 COUNTER 1 COUNTER 2
These three functional blocks are identical in opera-
tion so only a single Counter will be described The
internal block diagram of a single counter is shown
in Figure 5
The Counters are fully independent Each Counter
may operate in a different Mode
The Control Word Register is shown in the figure it
is not part of the Counter itself but its contents de-
termine how the Counter operates
3


3Pages


82C54 電子部品, 半導体
82C54
Write Operations
The programming procedure for the 82C54 is very
flexible Only two conventions need to be remem-
bered
1) For each Counter the Control Word must be
written before the initial count is written
2) The initial count must follow the count format
specified in the Control Word (least significant
byte only most significant byte only or least sig-
nificant byte and then most significant byte)
Since the Control Word Register and the three
Counters have separate addresses (selected by the
A1 A0 inputs) and each Control Word specifies the
Counter it applies to (SC0 SC1 bits) no special in-
struction sequence is required Any programming
sequence that follows the conventions above is ac-
ceptable
A new initial count may be written to a Counter at
any time without affecting the Counter’s pro-
grammed Mode in any way Counting will be affected
as described in the Mode definitions The new count
must follow the programmed count format
If a Counter is programmed to read write two-byte
counts the following precaution applies A program
must not transfer control between writing the first
and second byte to another routine which also writes
into that same Counter Otherwise the Counter will
be loaded with an incorrect count
A1 A0
Control Word Counter 0 1
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
Control Word Counter 1 1
1
LSB of count Counter 1 0
1
MSB of count Counter 1 0
1
Control Word Counter 2 1
1
LSB of count Counter 2 1
0
MSB of count Counter 2 1
0
A1 A0
Control Word Counter 2 1
1
Control Word Counter 1 1
1
Control Word Counter 0 1
1
LSB of count Counter 2 1
0
MSB of count Counter 2 1
0
LSB of count Counter 1 0
1
MSB of count Counter 1 0
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
A1 A0
Control Word Counter 0 1
1
Counter Word Counter 1 1
1
Control Word Counter 2 1
1
LSB of count Counter 2 1
0
LSB of count Counter 1 0
1
LSB of count Counter 0 0
0
MSB of count Counter 0 0
0
MSB of count Counter 1 0
1
MSB of count Counter 2 1
0
A1 A0
Control Word Counter 1 1
1
Control Word Counter 0 1
1
LSB of count Counter 1 0
1
Control Word Counter 2 1
1
LSB of count Counter 0 0
0
MSB of count Counter 1 0
1
LSB of count Counter 2 1
0
MSB of count Counter 0 0
0
MSB of count Counter 2 1
0
NOTE
In all four examples all counters are programmed to read write two-byte counts
These are only four of many possible programming sequences
Figure 8 A Few Possible Programming Sequences
Read Operations
It is often desirable to read the value of a Counter
without disturbing the count in progress This is easi-
ly done in the 82C54
There are three possible methods for reading the
counters a simple read operation the Counter
Latch Command and the Read-Back Command
Each is explained below The first method is to per-
form a simple read operation To read the Counter
which is selected with the A1 A0 inputs the CLK
input of the selected Counter must be inhibited by
using either the GATE input or external logic Other-
wise the count may be in the process of changing
when it is read giving an undefined result
6

6 Page



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