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82503 の電気的特性と機能

82503のメーカーはIntel Corporationです、この部品の機能は「DUAL SERIAL TRANSCEIVER (DST)」です。


製品の詳細 ( Datasheet PDF )

部品番号 82503
部品説明 DUAL SERIAL TRANSCEIVER (DST)
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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82503 Datasheet, 82503 PDF,ピン配置, 機能
82503
DUAL SERIAL TRANSCEIVER (DST)
82503 PRODUCT FEATURE SET OVERVIEW
Y Single Component Ethernet Interface
to Both 802 3 10BASE-T and AUI
Y Automatic or Manual Port Selection
Y Manchester Encoder Decoder and
Clock Recovery
Y No Glue Interface to Industry-Standard
LAN Controllers
Intel 82586 82590 82593 and 82596
AMD 7990 (LANCE )
National Semiconductor 8390 and
83932 (SONIC )
Western Digital 83C690
Fujitsu 86950 (Etherstar )
Y Diagnostic Loopback
Y Reset Low Power Modes
Y Network Status Indicators
Y Defeatable Jabber Timer
Y User Test Modes
Y 10 MHz Transmit Clock Generator
Y One Micron CHMOS IV (Px48)
Technology
Y Single 5-V Supply
INTERFACE FEATURES
TPE
Y Complies with 10BASE-T IEEE Std
802 3i-1990 for Twisted Pair Ethernet
Y Selectable Polarity Switching
Y Direct Interface to TPE Analog Filters
Y On-Chip TPE Squelch
Y Defeatable Link Integrity (LI)
Y Support of Cable Lengths l100m
AUI
Y Complies with IEEE 802 3 AUI Standard
Y Direct Interface to AUI Transformers
Y On-Chip AUI Squelch
A block diagram of a typical application is shown in Figure 1 The 82503 Dual Serial Transceiver is a high-inte-
gration CMOS device designed to simplify interfacing industry standard Ethernet LAN Controllers to IEEE
802 3 local area network applications (10BASE5 10BASE2 and 10BASE-T) The component supports both
an attachment unit interface (AUI) and a Twisted Pair Ethernet interface (TPE) It allows OEMs to design a
state-of-the-art media interface that is jumperless and fully automatic The 82503 includes on-chip AUI and
TPE drivers and receivers it offers designers a cost-effective integrated solution for interfacing LAN control-
lers to the wire medium
CHMOS is a patented process of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
LANCE is a registered trademark of Advanced Micro Devices
Etherstar is a registered trademark of Fujitsu Electronics
Sonic is a registered trademark of National Semiconductor Corporation
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT INTEL CORPORATION 1996
October 1995
Order Number 290421-004

1 Page





82503 pdf, ピン配列
82503
Figure 1 Application Block Diagram
290421 – 1
1 0 82503 PRODUCT FEATURES
The 82503 incorporates all the active circuitry re-
quired to interface Ethernet controllers to 10BASE-T
networks or the attachment unit interface (AUI) It
supports a direct no-glue interface to Intel’s family of
high-performance LAN controllers (82586 82590
82593 and 82596) The 82503 also provides a di-
rect no-glue interface to the National Semiconductor
8390 and 83932 (SONIC) the Western Digital
83C690 the Advanced Micro Devices 7990
(LANCE) and 79C900 (ILACC) and the Fujitsu
86950 (Etherstar) controllers
This component includes three advanced features
jumperless two-port design capability automatic port
selection and polarity switching The jumperless
TPE or AUI port selection capability allows design-
ers maximum ease-of-use and network flexibility Au-
tomatic port selection ensures complete software
compatibility with existing 10BASE2 and 10BASE5
software drivers The 82503’s polarity switching fea-
ture will detect and correct polarity errors on the
twisted pair the most common wiring fault in twist-
ed pair networks
The 82503 contains all the circuitry needed to meet
the 10BASE-T specification including link integrity a
jabber timer and internal predistortion Deselecting
link integrity allows the component to be used in
some prestandard networks The 82503’s jabber
timer prevents the station from continuously trans-
mitting and is defeatable for simple design charac-
terization The predistortion circuitry eliminates line
overcharge and reduces jitter on 10BASE-T links
The 82503 can also support twisted pair cable
lengths of up to 200m when placed in TPE Extended
Squelch Mode (XSQ)
This component incorporates six LED drivers to dis-
play transmit data receive data collision link integri-
ty polarity faults and port selections allowing for
complete network monitoring by the user The trans-
mit receive and collision LEDs indicate the rate of
activity by the frequency of flashing The 82503 also
has a low power mode During low power many of
the 82503’s pins are in a high-impedance state to
facilitate board-level testing
The 82503’s diagnostic loopback control enables it
to route a transmission signal from the LAN control-
ler through its Manchester encoder-decoder circuitry
and back to the LAN controller This provides effec-
tive network node fault detection and isolation capa-
bilities In addition the 82503 supports diagnostic
test modes that generate continuous tranmission of
data through the twisted pair port allowing design-
ers to measure the analog performance of their de-
sign
The 82503 is available in 44-lead PLCC and 44-lead
QFP packages and is fabricated with Intel’s low-
power high-speed CHMOS IV technology using a
single 5-V supply
3


3Pages


82503 電子部品, 半導体
82503
2 1 Power Pins
Symbol
PLCC
Pin
VSS(1)
VCC(1)
VCCA(1)
VSSA(1)
7 17 39
6 18 40
28
29
QFP
Pin
1 11 33
44 12 34
22
23
Type
Supply
Supply
Supply
Supply
Name and Function
Digital Ground
Digital VCC A 5-V g 5% Power Supply
Analog VCC A 5-V g 5% Power Supply
Analog Ground
NOTE
1 VCC and VCCA must be connected to the same power supply VSS and VSSA must be connected to the same ground
Separate decoupling and noise conditioning (e g ferrite beads) should be used
2 2 Clock Pins
Symbol
PLCC
Pin
QFP
Pin
X1 21 15
X2 20 14
Type
I
O
Name and Function
CLOCK CRYSTAL A 20 MHz crystal input This pin can be driven
with an external MOS level clock when X2 is left floating
CLOCK CRYSTAL A 20 MHz crystal output X1 can be driven with
an external MOS level clock when this pin is left floating
2 3 AUI Pins
Symbol
PLCC
Pin
TRMT
TRMT
27
26
RCV
RCV
31
30
CLSN
CLSN
25
24
QFP
Pin
21
20
25
24
19
18
Type
O
O
I
I
I
I
Name and Function
TRANSMIT PAIR A differential output driver pair that drives the
transmit pair of the transceiver cable The output bit stream is
Manchester encoded Following the last transition which is positive
at TRMT the differential voltage is reduced to zero volts
RECEIVE PAIR A differentially driven input pair which is tied to the
receive pair of the Ethernet transceiver cable The first transition on
RCV is negative-going to indicate the beginning of the frame The
last transition is positive-going to indicate the end of the frame The
received bit stream is assumed to be Manchester encoded
COLLISION PAIR A differentially driven input pair tied to the
collision presence pair of the Ethernet transceiver cable The
collision presence signal is a 10 MHz square wave The first
transition at CLSN is negative-going to indicate the beginning of the
signal the last transition is positive-going to indicate the end of the
signal
6

6 Page



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