82443LX Datasheet PDF - Intel Corporation
| Part Number | 82443LX | |
| Description | INTEL 440LX AGPSET: 82443LX PCI A.G.P. CONTROLLER (PAC) | |
| Manufacturers | Intel Corporation | |
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INTEL 440LX AGPSET: 82443LX PCI
A.G.P. CONTROLLER (PAC)
T Supports the Pentium® II Processor at
a Bus Frequency of 66 MHz
Supports 32-Bit Addressing
Optimized In-Order and Request
Queue
Full Symmetric Multi-Processor
(SMP) Protocol for Up to Two
Processors
Dynamic Deferred Transaction
Support
GTL+ Compliant Host Bus
Supports WC Cycles
T Integrated DRAM Controller
EDO (Extended Data Out), and
Synchronous DRAM Support
Supports a Maximum Memory Size
of 512 MB With SDRAM, or 1 GB
With EDO
64/72-bit Path to Memory
Configurable DRAM Interface
Support for Auto Detection of
Memory Type: (DIMM Serial
Presence Detect)
8 RAS Lines Available
Support for 4-, 16- and 64-Mbit
DRAM devices
Support for Symmetrical and
Asymmetrical DRAM Addressing
Configurable Support for ECC/EC
ECC With Single Bit Error
Correction and Multiple Bit Error
Detection
Read-Around-Write Support for
Host and PCI DRAM Read Accesses
Supports 3.3V DRAMs
T Accelerated Graphics Port (A.G.P.)
Interface
A.G.P. Specification Compliant
A.G.P. 66/133 MHz 3.3V Devices
Supported
Synchronous Coupling to the Host
Bus Frequency
T PCI Bus Interface
PCI Revision 2.1 Interface
Compliant
Greater Than 100-MBps Data
Streaming for PCI-to-DRAM
Accesses
Integrated Arbiter With Multi-
Transaction PCI Arbitration
Acceleration Hooks
Five PCI Bus Masters are Supported
in Addition to the Host and PCI-to-
ISA I/O Bridge
Delayed Transaction Support
PCI Parity Checking and Generation
Support
T Data Buffering For Increased
Performance
Extensive CPU-to-DRAM, PCI-to-
DRAM, and A.G.P.-to-DRAM Write
Data Buffering
CPU-to-A.G.P., PCI-to-A.G.P., and
A.G.P.-to-PCI Data Buffering
Write Combining Support for
CPU-to-PCI Burst Writes
Supports Concurrent Host, PCI, and
A.G.P. Transactions to Main
Memory
T System Management Mode (SMM)
Compliant
T 492 Pin BGA Package
The 82443LX (PAC) is the first generation of desktop AGPset designed for the Pentium® II processor. The
82443LX PCI A.G.P. Controller (PAC) integrates a Host-to-PCI bridge, optimized DRAM controller and data
path, and an Accelerated Graphics Port (A.G.P.) interface. A.G.P. is a high performance, component level
interconnect, targeted at 3D graphics applications and based on a set of performance enhancements to PCI.
The I/O subsystem portion of the PAC platform is based on the PIIX4, a highly integrated version of the
Intel’s PCI-to-ISA bridge family. PAC is developed as the ultimate Pentium II processor platform and is
targeted for emerging 3D graphics and multimedia applications. The 440LX AGPset may contain design
defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request.
January 1998
Order Number: 290564-002
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INTEL 82443LX (PAC)
3.3.19. FDHC—FIXED DRAM HOLE CONTROL REGISTER (DEVICE 0) ............................................ 50
3.3.20. DRAMXC—DRAM EXTENDED CONTROL REGISTER (DEVICE 0) ........................................ 51
3.3.21. MBSC—MEMORY BUFFER STRENGTH CONTROL REGISTER (DEVICE 0)......................... 52
3.3.22. MTT—MULTI-TRANSACTION TIMER REGISTER (DEVICE 0) ................................................ 54
3.3.23. SMRAM—SYSTEM MANAGEMENT RAM CONTROL REGISTER (DEVICE 0) ....................... 55
3.3.24. ERRCMD—ERROR COMMAND REGISTER (DEVICE 0)......................................................... 56
3.3.25. ERRSTS0—ERROR STATUS REGISTER 0 (DEVICE 0).......................................................... 57
3.3.26. ERRSTS1—ERROR STATUS REGISTER 1 (DEVICE 0).......................................................... 59
3.3.27. RSTCTRL—RESET CONTROL REGISTER (DEVICE 0) .......................................................... 60
3.3.28. ACAPID—A.G.P. CAPABILITY IDENTIFIER REGISTER (DEVICE 0)....................................... 61
3.3.29. AGPSTAT—A.G.P. STATUS REGISTER (DEVICE 0) .............................................................. 62
3.3.30. AGPCMD—A.G.P. COMMAND REGISTER (DEVICE 0)........................................................... 62
3.3.31. AGPCTRL—A.G.P. CONTROL REGISTER (DEVICE 0) ........................................................... 63
3.3.32. APSIZE—APERTURE SIZE (DEVICE 0)................................................................................... 64
3.3.33. ATTBASE—APERTURE TRANSLATION TABLE BASE REGISTER (DEVICE 0)..................... 65
3.3.34. AMTT—A.G.P. INTERFACE MULTI-TRANSACTION TIMER REGISTER (DEVICE 0) ............. 65
3.3.35. LPTT—LOW PRIORITY TRANSACTION TIMER REGISTER (DEVICE 0)................................ 65
3.4. A.G.P. Configuration Registers—(Device 1) ....................................................................................... 66
3.4.1. VID1—VENDOR IDENTIFICATION REGISTER (DEVICE 1) ...................................................... 66
3.4.2. DID1—DEVICE IDENTIFICATION REGISTER (DEVICE 1) ........................................................ 66
3.4.3. PCICMD1—PCI-PCI COMMAND REGISTER (DEVICE 1) .......................................................... 66
3.4.4. PCISTS1—PCI-PCI STATUS REGISTER (DEVICE 1)................................................................ 67
3.4.5. RID1—REVISION IDENTIFICATION REGISTER (DEVICE 1) .................................................... 67
3.4.6. SUBC1—SUB-CLASS CODE REGISTER (DEVICE 1) ............................................................... 67
3.4.7. BCC1—BASE CLASS CODE REGISTER (DEVICE 1)................................................................ 68
3.4.8. HDR1—HEADER TYPE REGISTER (DEVICE 1)........................................................................ 68
3.4.9. PBUSN—PRIMARY BUS NUMBER REGISTER—DEVICE #1 ................................................... 68
3.4.10. SBUSN—SECONDARY BUS NUMBER REGISTER (DEVICE 1) ............................................. 69
3.4.11. SUBUSN—SUBORDINATE BUS NUMBER REGISTER (DEVICE 1)........................................ 69
3.4.12. SMLT—SECONDARY MASTER LATENCY TIMER REGISTER (DEVICE 1)............................ 69
3.4.13. IOBASE—I/O BASE ADDRESS REGISTER (DEVICE 1) .......................................................... 70
3.4.14. IOLIMIT—I/O LIMIT ADDRESS REGISTER (DEVICE 1)........................................................... 70
3.4.15. SSTS—SECONDARY PCI-PCI STATUS REGISTER (DEVICE 1) ............................................ 71
3.4.16. MBASE—MEMORY BASE ADDRESS REGISTER (DEVICE 1)................................................ 72
3.4.17. MLIMIT—MEMORY LIMIT ADDRESS REGISTER (DEVICE 1) ................................................ 72
3.4.18. PMBASE—PREFETCHABLE MEMORY BASE ADDRESS REGISTER (DEVICE 1) ................ 73
3.4.19. PMLIMIT—PREFETCHABLE MEMORY LIMIT ADDRESS REGISTER (DEVICE 1) ................. 73
3.4.20. BCTRL—PCI-PCI BRIDGE CONTROL REGISTER (DEVICE 1) ............................................... 74
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