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82434NX の電気的特性と機能

82434NXのメーカーはIntel Corporationです、この部品の機能は「PCI/ CACHE AND MEMORY CONTROLLER PCMC」です。


製品の詳細 ( Datasheet PDF )

部品番号 82434NX
部品説明 PCI/ CACHE AND MEMORY CONTROLLER PCMC
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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82434NX Datasheet, 82434NX PDF,ピン配置, 機能
82434LX 82434NX PCI CACHE AND MEMORY
CONTROLLER (PCMC)
Y Supports the PentiumTM Processor at
iCOMPTM Index 510T60 MHz and iCOMP
Index 567T66 MHz
Y Supports the Pentium Processor at
iCOMP Index 735T90 MHz iCOMP Index
815T100 MHz and iCOMP Index 610T75
MHz
Y Supports Pipelined Addressing
Capability of the Pentium Processor
Y The 82430NX Drives 3 3V Signal Levels
on the CPU and Cache Interfaces
Y High Performance CPU PCI Memory
Interfaces via Posted Write and Read
Prefetch Buffers
Y Fully Synchronous PCI Interface with
Full Bus Master Capability
Y Supports the Pentium Processor
Internal Cache in Either Write-Through
or Write-Back Mode
Y Programmable Attribute Map of DOS
and BIOS Regions for System
Flexibility
Y Integrated Low Skew Clock Driver for
Distributing Host Clock
Y Integrated Second Level Cache
Controller
Integrated Cache Tag RAM
Write-Through and Write-Back Cache
Modes for the 82434LX
Write-Back for the 82434NX
82434NX Supports Low-Power Cache
Standby
Direct Mapped Organization
Supports Standard and Burst SRAMs
256-KByte and 512-KByte Sizes
Cache Hit Cycle of 3-1-1-1 on Reads
and Writes Using Burst SRAMs
Cache Hit Cycle of 3-2-2-2 on Reads
and 4-2-2-2 on Writes Using
Standard SRAMs
Y Integrated DRAM Controller
Supports 2 MBytes to 192 MBytes of
Cacheable Main Memory for the
82434LX
Supports 2 MBytes to 512 MBytes of
Cacheable Main Memory for the
82434NX
Supports DRAM Access Times of
70 ns and 60 ns
CPU Writes Posted to DRAM 4-1-1-1
Refresh Cycles Decoupled from ISA
Refresh to Reduce the DRAM
Access Latency
Six RAS Lines (82434LX)
Eight RAS Lines (82434NX)
Refresh by RAS -Only or CAS-
Before-RAS in Single or Burst
of Four
Y Host PCI Bridge
Translates CPU Cycles into PCI Bus
Cycles
Translates Back-to-Back Sequential
CPU Memory Writes into PCI Burst
Cycles
Burst Mode Writes to PCI in Zero PCI
Wait-States (i e Data Transfer Every
Cycle)
Full Concurrency Between CPU-to-
Main Memory and PCI-to-PCI
Transactions
Full Concurrency Between CPU-to-
Second Level Cache and PCI-to-Main
Memory Transactions
Same Cache and Memory System
Logic Design for ISA and EISA
Systems
Cache Snoop Filter Ensures Data
Consistency for PCI-to-Main Memory
Transactions
Y 208-Pin QFP Package
Other brands and names are the property of their respective owners
December 1994
Order Number 290479-004

1 Page





82434NX pdf, ピン配列
82434LX 82434NX
NOTE
RAS 7 6 and MA11 are only on the 82434NX CCS 1 0 functionality is only on the 82434NX
Simplified Block Diagram of the PCMC
290479 – 1
3


3Pages


82434NX 電子部品, 半導体
CONTENTS
5 0 SECOND LEVEL CACHE INTERFACE
5 1 82434LX Cache
5 1 1 CLOCK LATENCIES (82434LX)
5 1 2 STANDARD SRAM CACHE CYCLES (82434LX)
5 1 2 1 Burst Read (82434LX)
5 1 2 2 Burst Write (82434LX)
5 1 2 3 Cache Line Fill (82434LX)
5 1 3 BURST SRAM CACHE CYCLES (82434LX)
5 1 3 1 Burst Read (82434LX)
5 1 3 2 Burst Write (82434LX)
5 1 3 3 Cache Line Fill (82434LX)
5 1 4 SNOOP CYCLES
5 1 5 FLUSH FLUSH ACKNOWLEDGE AND WRITE-BACK SPECIAL CYCLES
5 2 82434NX Cache
5 2 1 CYCLE LATENCY SUMMARY (82434NX)
5 2 2 STANDARD SRAM CACHE CYCLES (82434NX)
5 2 3 SECOND LEVEL CACHE STANDBY
5 2 4 SNOOP CYCLES
5 2 5 FLUSH FLUSH ACKNOWLEDGE AND WRITE-BACK SPECIAL CYCLES
6 0 DRAM INTERFACE
6 1 82434LX DRAM Interface
6 1 1 DRAM CONFIGURATIONS
6 1 2 DRAM ADDRESS TRANSLATION
6 1 3 CYCLE TIMING SUMMARY
6 1 4 CPU TO DRAM BUS CYCLES
6 1 4 1 Read Page Hit
6 1 4 2 Read Page Miss
6 1 4 3 Read Row Miss
6 1 4 4 Write Page Hit
6 1 4 5 Write Page Miss
6 1 4 6 Write Row Miss
6 1 4 7 Read Cycle 0-Active RAS Mode
6 1 4 8 Write Cycle 0-Active RAS Mode
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ページ 合計 : 30 ページ
 
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[ 82434NX データシート.PDF ]


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共有リンク

Link :


部品番号部品説明メーカ
82434NX

PCI/ CACHE AND MEMORY CONTROLLER PCMC

Intel Corporation
Intel Corporation


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