DataSheet.jp

82433LX の電気的特性と機能

82433LXのメーカーはIntel Corporationです、この部品の機能は「LOCAL BUS ACCELERATOR (LBX)」です。


製品の詳細 ( Datasheet PDF )

部品番号 82433LX
部品説明 LOCAL BUS ACCELERATOR (LBX)
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




このページの下部にプレビューと82433LXダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

82433LX Datasheet, 82433LX PDF,ピン配置, 機能
82433LX 82433NX
LOCAL BUS ACCELERATOR (LBX)
Y Supports the Full 64-bit Pentium
Processor Data Bus at Frequencies up
to 66 MHz (82433LX and 82433NX)
Y Drives 3 3V Signal Levels on the CPU
Data and Address Buses (82433NX)
Y Provides a 64-Bit Interface to DRAM
and a 32-Bit Interface to PCI
Y Five Integrated Write Posting and Read
Prefetch Buffers Increase CPU and PCI
Performance
CPU-to-Memory Posted Write Buffer
4 Qwords Deep
PCI-to-Memory Posted Write Buffer
Two Buffers 4 Dwords Each
PCI-to-Memory Read Prefetch Buffer
4 Qwords Deep
CPU-to-PCI Posted Write Buffer
4 Dwords Deep
CPU-to-PCI Read Prefetch Buffer
4 Dwords Deep
Y CPU-to-Memory and CPU-to-PCI Write
Posting Buffers Accelerate Write
Performance
Y Dual-Port Architecture Allows
Concurrent Operations on the Host and
PCI Buses
Y Operates Synchronously to the CPU
and PCI Clocks
Y Supports Burst Read and Writes of
Memory from the Host and PCI Buses
Y Sequential CPU Writes to PCI
Converted to Zero Wait-State PCI
Bursts with Optional TRDY
Connection
Y Byte Parity Support for the Host and
Memory Buses
Optional Parity Generation for Host
to Memory Transfers
Optional Parity Checking for the
Secondary Cache
Parity Checking for Host and PCI
Memory Reads
Parity Generation for PCI to Memory
Writes
Y 160-Pin QFP Package
Two 82433LX or 82433NX Local Bus Accelerator (LBX) components provide a 64-bit data path between the
host CPU Cache and main memory a 32-bit data path between the host CPU bus and PCI Local Bus and a
32-bit data path between the PCI Local Bus and main memory The dual-port architecture allows concurrent
operations on the host and PCI Buses The LBXs incorporate three write posting buffers and two read prefetch
buffers to increase CPU and PCI performance The LBX supports byte parity for the host and main memory
buses The 82433NX is intended to be used with the 82434NX PCI Cache Memory Controller (PCMC) The
82433LX is intended to be used with the 82434LX PCMC During bus operations between the host main
memory and PCI the PCMC commands the LBXs to perform functions such as latching address and data
merging data and enabling output buffers Together these three components form a ‘‘Host Bridge’’ that
provides a full function dual-port data path interface linking the host CPU and PCI bus to main memory
This document describes both the 82433LX and 82433NX Shaded areas like this one describe the
82433NX operations that differ from the 82433LX
December 1995
Order Number 290478-004

1 Page





82433LX pdf, ピン配列
82433LX 82433NX
LOCAL BUS ACCELERATOR (LBX)
CONTENTS
1 0 ARCHITECTURAL OVERVIEW
1 1 Buffers in the LBX
1 2 Control Interface Groups
1 3 System Bus Interconnect
1 4 PCI TRDY Interface
1 5 Parity Support
2 0 SIGNAL DESCRIPTIONS
2 1 Host Interface Signals
2 2 Main Memory (DRAM) Interface Signals
2 3 PCI Interface Signals
2 4 PCMC Interface Signals
2 5 Reset and Clock Signals
3 0 FUNCTIONAL DESCRIPTION
3 1 LBX Post and Prefetch Buffers
3 1 1 CPU-TO-MEMORY POSTED WRITE BUFFER
3 1 2 PCI-TO-MEMORY POSTED WRITE BUFFER
3 1 3 PCI-TO-MEMORY READ PREFETCH BUFFER
3 1 4 CPU-TO-PCI POSTED WRITE BUFFER
3 1 5 CPU-TO-PCI READ PREFETCH BUFFER
3 2 LBX Interface Command Descriptions
3 2 1 HOST INTERFACE GROUP HIG 4 0
3 2 2 MEMORY INTERFACE GROUP MIG 2 0
3 2 3 PCI INTERFACE GROUP PIG 3 0
3 3 LBX Timing Diagrams
3 3 1 HIG 4 0 COMMAND TIMING
3 3 2 HIG 4 0 MEMORY READ TIMING
3 3 3 MIG 2 0 COMMAND
3 3 4 PIG 3 0 COMMAND DRVPCI AND PPOUT TIMING
3 3 5 PIG 3 0 READ PREFETCH BUFFER COMMAND TIMING
3 3 6 PIG 3 0 END-OF-LINE WARNING SIGNAL EOL
3 4 PLL Loop Filter Components
3 5 PCI Clock Considerations
PAGE
5
5
7
7
8
8
8
9
10
10
10
11
12
12
12
12
12
13
14
14
14
18
19
21
21
22
23
24
25
27
29
30
3


3Pages


82433LX 電子部品, 半導体
82433LX 82433NX
290478 – 2
NOTES
1 CPU-to-Memory Posted Write Buffer This buffer is 4 Qwords deep enabling the Pentium processor to write back a
whole cache line in 4-1-1-1 timing a total of 7 CPU clocks
2 PCI-to-Memory Posted Write Buffer A PCI master can post two consecutive sets of 4 Dwords (total of one cache
line) or two single non-consecutive transactions
3 PCI-to-Memory Read Prefetch Buffer A PCI master to memory read transaction will cause this prefetch buffer to
read up to 4 Qwords of data from memory allowing up to 8 Dwords to be read onto PCI in a single burst transaction
4 CPU-to-PCI Posted Write Buffer The Pentium processor can post up to 4 Dwords into this buffer The TRDY
connect option allows zero-wait state burst writes to PCI making this buffer especially useful for graphic write
operations
5 CPU-to-PCI Read Prefetch Buffer This prefetch buffer is 4 Dwords deep enabling faster sequential Pentium proc-
essor reads when targeting PCI
Figure 1 Simplified Block Diagram of the LBX Data Buffers
6

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ 82433LX データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
82433LX

LOCAL BUS ACCELERATOR (LBX)

Intel Corporation
Intel Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap