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MK2049-34A の電気的特性と機能

MK2049-34AのメーカーはIntegrated Circuit Systemsです、この部品の機能は「3.3 Volt Communications Clock VCXO PLL」です。


製品の詳細 ( Datasheet PDF )

部品番号 MK2049-34A
部品説明 3.3 Volt Communications Clock VCXO PLL
メーカ Integrated Circuit Systems
ロゴ Integrated Circuit Systems ロゴ 




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MK2049-34A Datasheet, MK2049-34A PDF,ピン配置, 機能
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Description
The MK2049-34A is a VCXO Phased Locked Loop
(PLL) based clock synthesizer that accepts multiple
input frequencies. With an 8 kHz clock input as a
reference, the MK2049-34A generates T1, E1, T3, E3,
ISDN, xDSL, and other communications frequencies.
This allows for the generation of clocks
frequency-locked and phase-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems. The MK2409-34 can also
accept a T1 or E1 input clock and provide the same
output for loop timing. All outputs are frequency locked
together and to the input.
This part also has a jitter-attenuated Buffer capability.
In this mode, the MK2049-34A is ideal for filtering jitter
from 27 MHz video clocks or other clocks with high
jitter.
ICS can customize these devices for many other
different frequencies.
Features
Packaged in 20-pin SOIC
3.3 V + 5% operation
Fixed I/O phase relationship on all selections
Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4,
and 4E
Accepts multiple inputs: 8 kHz backplane clock, Loop
Timing frequencies, or 10 to 36 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 to 36 MHz
input and x1/x0.5 or x2/x4 outputs
Exact internal ratios enable zero ppm error
Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and the OC3 submultiples
See the MK2049-01, -02, and -03 for more selections
at 5 V
Block Diagram
INPUT REFERENCE
CLOCK
(TYPICALLY 8KHZ)
4
FREQUENCY SELECT
EXTERNAL PULLABLE CRYSTAL
(external loop filter)
VCXO-BASED
PLL
(MASTER CLOCK
GENERATOR)
FREQUENCY
MULTIPLYING
PLL
2
CLOCK OUTPUT
CLOCK OUTPUT / 2
8 KHZ (REGENERATED)
MDS 2049-34A A
1
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com

1 Page





MK2049-34A pdf, ピン配列
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
Output Decoding Table - External Mode (MHz)
ICLK FS3 FS2 FS1 FS0
8 kHz 0 0 0 0
8 kHz 0 0 0 1
8 kHz 0 0 1 0
8 kHz 0 0 1 1
8 kHz 0 1 0 0
8 kHz 0 1 0 1
8 kHz 0 1 1 0
8 kHz 0 1 1 1
8 kHz 1 0 1 0
8 kHz 1 0 1 1
8 kHz 1 1 0 0
8 kHz 1 1 0 1
CLK/2
1.544
2.048
22.368
17.184
19.44
16.384
17.664
18.688
7.68
10.752
10.24
38.88
CLK
3.088
4.096
44.736
34.368
38.88
32.768
35.328
37.376
15.36
21.504
20.48
77.76
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
Crystal
Used (MHz)
12.352
12.288
11.184
11.456
9.72
8.192
17.664
9.344
15.36
10.752
10.24
9.72
Output Decoding Table - Loop Timing Mode (MHz)
N
1544
1536
1398
1432
1215
1024
2208
1168
1920
1344
1280
1215
ICLK FS3 FS2 FS1 FS0 CLK/2
CLK
1.544
1
0
0
0
1.544
3.088
2.048
1
0
0
1
2.048
4.096
8k Crystal
N/A 12.352
N/A 12.288
N
24
18
Output Decoding Table - Buffer Mode (MHz)
ICLK FS3 FS2 FS1 FS0 CLK/2
CLK
8k Crystal
19 - 36
1
1
1
0
ICLK/2
ICLK
N/A ICLK/2
10 - 18
1
1
1
1 2*ICLK 4*ICLK N/A
ICLK
N
3
3
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Operating Modes
The MK2049-34A has three operating modes: External, Loop Timing, and Buffer. Although each mode uses an
input clock to generate various output clocks, there are important differences in their input and crystal
requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication clock
frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse as narrow as 10
ns is acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned with the rising edge of the
8 kHz ICLK; refer to Figure 1 on page 4 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1 and E1
inputs, the CLK/2 output will be the same as the input frequency, with CLK at twice the input frequency.
MDS 2049-34A A
3
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com


3Pages


MK2049-34A 電子部品, 半導体
MK2049-34A
3.3 Volt Communications Clock VCXO PLL
External Component Selection
The MK2049-34A requires a minimum number of external components for proper operation. Decoupling capacitors
of 0.01µF must be connected between VDD and GND pins close to the chip (especially pins 4 and 7, 15 and 17),
and 33series terminating resistors should be used on clock outputs with traces longer than one inch (assuming
50traces). The selection of additional external components is described in the following sections.
Loop Filter
Information on how to configure the external loop filter, connected between pins CAP1 and CAP2, can be found at
http://www.icst.com/products/telecom/telecom.htm and http://www.icst.com/PDF/MK2049-3x%20Addendum.pdf.
Crystal Operation
The MK2049-34A operates by phase locking the input signal to a VCXO which consists of the recommended
pullable VCXO crystals and the integrated VCXO oscillator circuit on the MK2049-34A. To achieve the best
performance and reliability, the layout guidelines shown on the previous page should be closely followed.
The frequency of oscillation of a quartz crystal is determined by its cut and by the load capacitors connected to it.
The MK2049-34A has variable load capacitors on-chip which “pull” or change the frequency of the crystal. External
stray capacitance must be kept to a minimum to ensure maximum pullability of the crystal. To achieve this, the
layout should use short traces between the MK2049-34A and the crystal.
For the VCXO to operate correctly, a pullable crystal must be used. For more information, including a list of
approved crystals, please refer to application note MAN05 (http://www.icst.com/products/summary/man05.htm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-34A. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Rating
7V
-0.5 V to VDD+0.5 V
-40 to +85°C
-65 to +150°C
175°C
250°C
MDS 2049-34A A
6
Revision 032504
Integrated Circuit Systems, Inc. z 525 Race Street, San Jose, CA 95126 z tel (408) 297-1201 z www.icst.com

6 Page



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部品番号部品説明メーカ
MK2049-34

3.3 V Communications Clock PLL

Integrated Circuit Systems
Integrated Circuit Systems
MK2049-34A

3.3 Volt Communications Clock VCXO PLL

Integrated Circuit Systems
Integrated Circuit Systems


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