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PDF MK2049-34 Data sheet ( Hoja de datos )
| Número de pieza | MK2049-34 | |
| Descripción | 3.3 V Communications Clock PLL | |
| Fabricantes | Integrated Circuit Systems | |
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MK2049-34
3.3 V Communications Clock PLL
Description
Features
The MK2049-34 is a Phase-Locked Loop (PLL)
based clock synthesizer that accepts multiple input
frequencies. With an 8 kHz clock input as a
reference, the MK2049-34 generates T1, E1, T3,
E3, ISDN, xDSL, and other communications
frequencies. This allows for the generation of
clocks frequency-locked and phase-locked to an
8 kHz backplane clock, simplifying clock
synchronization in communications systems. The
MK2049-34 can also accept a T1 or E1 input clock
and provide the same output for loop timing. All
outputs are frequency locked together and to the
input.
This part also has a jitter-attenuated Buffer
capability. In this mode, the MK2049-34 is ideal
for filtering jitter from 27 MHz video clocks or
other clocks with high jitter.
ICS/MicroClock can customize these devices for
many other different frequencies. Contact your
ICS/MicroClock representative for more details.
• Packaged in 20 pin SOIC
• 3.3 V ±5% operation
• Fixed I/O phase relationship on all selections
• Meets the TR62411, ETS300 011, and GR-1244
specification for MTIE, Pull-in/Hold-in Range,
Phase Transients, and Jitter Generation for
Stratum 3, 4, and 4E
• Accepts multiple inputs: 8 kHz backplane clock,
Loop Timing frequencies, or 10-36 MHz
• Locks to 8 kHz ±100 ppm (External mode)
• Buffer Mode allows jitter attenuation of
10–36 MHz input and x1/x0.5 or x2/x4 outputs
• Exact internal ratios enable zero ppm error
• Output clock rates include T1, E1, T3, E3, ISDN,
xDSL, and OC3 submultiples
• See the MK2049-01, -02, and -03 for more
selections at VDD = 5 V
Block Diagram
VDD
3
GND
3
RES
FS3:0 4
Clock
Input
Reference
Crystal X1
External/
Loop Timing
Mux
Crystal
Oscillator
X2
FCAP
PLL
Clock
Synthesis,
Control, and
Jitter
Attenuation
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CAP1
CAP2
CLK
CLK/2
8 kHz
(External
Mode only)
MDS 2049-34 C
1
Revision 121400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
1 page  
MK2049-34
3.3 V Communications Clock PLL
OPERATING MODES
The MK2049-34 has three operating modes: External, Loop Timing, and Buffer. Although each mode
uses an input clock to generate various output clocks, there are important differences in their input and
crystal requirements.
External Mode
The MK2049-34 accepts an external 8 kHz clock and will produce a number of common communication
clock frequencies. The 8 kHz input clock does not need to have a 50% duty cycle; a “high” or “on” pulse
as narrow as 10 ns is acceptable. In the MK2049-34, the rising edges of CLK and CLK/2 are both aligned
with the rising edge of the 8 kHz ICLK; refer to Figure 1 for more details.
Loop Timing Mode
This mode can be used to remove the jitter from standard high-frequency communication clocks. For T1
and E1 inputs, the CLK/2 output will be the same as the input frequency, with CLK at twice the input
frequency.
Buffer Mode
Unlike the other two modes that accept only a single specified input frequency, Buffer Mode will accept a
wider range of input clocks. The input jitter is attenuated, and the outputs on CLK and CLK/2 also
provide the option of getting x1, x2, x4, or 1/2 of the input frequency. For example, this mode can be
used to remove the jitter from a 27 MHz clock, generating low-jitter 27 MHz and 13.5 MHz outputs.
INPUT AND OUTPUT SYNCHRONIZATION
As shown in the tables on page 4, the MK2049-34 offers a Zero Delay feature in all selections. There is an
internal feedback path between ICLK and the output clocks, providing a fixed phase relationship between
the input and output, a requirement in many communications systems.
The rising edge of ICLK will be aligned with the rising edges of CLK and CLK/2. (8 kHz is used in this
illustration, but the same is true for the selections in the Loop Timing and Buffer modes.)
ICLK (8 kHz)
CLK (MHz)
CLK/2(MHz)
Figure 1. MK2049-34 Input and Output Clock Waveforms
MDS 2049-34 C
5
Revision 121400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
5 Page 
MK2049-34
3.3 V Communications Clock PLL
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
INDEX
AREA
12
D
EH
h x 45°
20 pin SOIC
Symbol
A
A1
B
C
D
E
e
H
h
L
Inches
Min Max
-- 0.104
0.0040 --
0.013 0.020
0.007 0.013
0.496 0.512
0.291 0.299
.050 BSC
0.394 0.419
0.01 0.029
0.016 0.050
Millimeters
Min Max
-- 2.65
0.10 --
0.33 0.51
0.18 0.33
12.60 13.00
7.40 7.60
1.27 BSC
10.01 10.64
0.25 0.74
0.41 1.27
A1
e
C
B
A
L
Ordering Information
Part/Order Number
MK2049-34SI
MK2049-34SITR
Marking
MK2049-34SI
MK2049-34SI
Package
20 pin SOIC
Add Tape & Reel
Temperature
-40 to 85 °C
-40 to 85 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
MDS 2049-34 C
11
Revision 121400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
11 Page | ||
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| PDF Descargar | [ Datasheet MK2049-34.PDF ] | |
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