DataSheet.jp

80960JD の電気的特性と機能

80960JDのメーカーはIntel Corporationです、この部品の機能は「EMBEDDED 32-BIT MICROPROCESSOR」です。


製品の詳細 ( Datasheet PDF )

部品番号 80960JD
部品説明 EMBEDDED 32-BIT MICROPROCESSOR
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




このページの下部にプレビューと80960JDダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

80960JD Datasheet, 80960JD PDF,ピン配置, 機能
www.DataSheet4U.com
A
PRELIMINARY
80960JD
EMBEDDED 32-BIT MICROPROCESSOR
s Pin/Code Compatible with all 80960Jx
s High Bandwidth Burst Bus
Processors
— 32-Bit Multiplexed Address/Data
s High-Performance Embedded Architecture
— One Instruction/Clock Execution
— Core Clock Rate is 2x the Bus Clock
— Load/Store Programming Model
— Sixteen 32-Bit Global Registers
— Sixteen 32-Bit Local Registers (8 sets)
— Nine Addressing Modes
— Programmable Memory Configuration
— Selectable 8-, 16-, 32-Bit Bus Widths
— Supports Unaligned Accesses
— Big or Little Endian Byte Ordering
s New Instructions
— Conditional Add, Subtract and Select
— Processor Management
— User/Supervisor Protection Model
s High-Speed Interrupt Controller
s Two-Way Set Associative Instruction Cache — 31 Programmable Priorities
— 80960JD - 4 Kbyte
— Programmable Cache Locking
— Eight Maskable Pins plus NMI
— Up to 240 Vectors in Expanded Mode
Mechanism
s Two On-Chip Timers
s Direct Mapped Data Cache
— Independent 32-Bit Counting
— 80960JD - 2 Kbyte
— Write Through Operation
— Clock Prescaling by 1, 2, 4 or 8
— lnternal Interrupt Sources
s On-Chip Stack Frame Cache
— Seven Register Sets Can Be Saved
— Automatic Allocation on Call/Return
— 0-7 Frames Reserved for High-Priority
Interrupts
s On-Chip Data RAM
— 1 Kbyte Critical Variable Storage
— Single-Cycle Access
s Halt Mode for Low Power
s IEEE 1149.1 (JTAG) Boundary Scan
Compatibility
s Packages
— 132-Lead Pin Grid Array (PGA)
— 132-Lead Plastic Quad Flat Pack (PQFP)
iA80960JD
XXXXXXXXA2
M © 19xx
PIN 1
132
33
A
i960®
iNG80960JD
XXXXXXXXA2
M © 19xx
99
66
Figure 1. 80960JD Microprocessor
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products. Information
contained herein supersedes previously published specifications on these devices from Intel.
© INTEL CORPORATION, 1995
September 1995
Order Number: 272596-002

1 Page





80960JD pdf, ピン配列
www.DataSheet4U.com
80960JD
A
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
80960JD Microprocessor ...........................................................................................................0
80960JD Block Diagram ............................................................................................................2
132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13
132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14
132-Lead PQFP - Top View ..................................................................................................... 17
50 MHz Maximum Allowable Ambient Temperature ................................................................ 21
40 MHz Maximum Allowable Ambient Temperature ................................................................ 22
AC Test Load ............................................................................................................................ 33
Output Delay or Hold vs. Load Capacitance ............................................................................ 33
Rise and Fall Time Derating ..................................................................................................... 34
CLKIN Waveform ..................................................................................................................... 34
Output Delay Waveform for TOV1 ............................................................................................. 35
Output Float Waveform for TOF ................................................................................................ 35
Input Setup and Hold Waveform for TIS1 and TIH1 ................................................................... 36
Input Setup and Hold Waveform for TIS2 and TIH2 ................................................................... 36
Input Setup and Hold Waveform for TIS3 and TIH3 ................................................................... 37
Input Setup and Hold Waveform for TIS4 and TIH4 ................................................................... 37
Relative Timings Waveform for TLXL and TLXA ......................................................................... 38
DT/R and DEN Timings Waveform .......................................................................................... 38
TCK Waveform ......................................................................................................................... 39
Input Setup and Hold Waveforms for TBSIS1 and TBSIH1 ......................................................... 39
Output Delay and Output Float Waveform for TBSOV1 and TBSOF1 .......................................... 40
Output Delay and Output Float Waveform for TBSOV2 and TBSOF2 .......................................... 40
Input Setup and Hold Waveform for TBSIS2 and TBSIH2 ........................................................... 41
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 42
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 44
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ................................................................................... 46
Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47
HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48
Cold Reset Waveform .............................................................................................................. 49
Warm Reset Waveform ............................................................................................................ 50
Entering the ONCE State ......................................................................................................... 51
Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 55
iii PRELIMINARY


3Pages


80960JD 電子部品, 半導体
www.DataSheet4U.com
80960JD
A
CLKIN
PLL, Clocks,
Power Mgmt
TAP Boundary Scan
5 Controller
8-Set
Local Register Cache
128
Global / Local
Register File
SRC1 SRC2 DEST
4 KByte Instruction Cache
Two-Way Set Associative
32-bit buses
address / data
Physical Region
Configuration
Bus
Control Unit
Bus Request
Queues
Control
21
Address/
Data Bus
32
Instruction Sequencer
Constants Control
Multiply
Divide
Unit
Execution
and
Address
Generation
Unit
effective
address
Memory
Interface
Unit
32-bit Address
32-bit Data
Two 32-Bit
Timers
Interrupt
Programmable Port
Interrupt Controller 9
Memory-Mapped
Register Interface
1 Kbyte
Data RAM
2 Kbyte Direct
Mapped Data
Cache
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
Figure 2. 80960JD Block Diagram
2.1 80960 Processor Core
The 80960Jx family is a scalar implementation of the
80960 Core Architecture. Intel designed this
processor core as a very high performance device
that is also cost-effective. Factors that contribute to
the core’s performance include:
• Core operates at twice the bus speed (80960JD
only)
• Single-clock execution of most instructions
• Independent Multiply/Divide Unit
• Efficient instruction pipeline minimizes pipeline
break latency
• Register and resource scoreboarding allow
overlapped instruction execution
• 128-bit register bus speeds local register caching
• 4 Kbyte two-way set associative, integrated
instruction cache
• 2 Kbyte direct-mapped, integrated data cache
• 1 Kbyte integrated data RAM delivers zero wait
state program data
2.2 Burst Bus
A 32-bit high-performance bus controller interfaces
the 80960JD to external memory and peripherals.
The BCU fetches instructions and transfers data at
the rate of up to four 32-bit words per six clock
cycles. The external address/data bus is multiplexed.
2 PRELIMINARY

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ 80960JD データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
80960JA

EMBEDDED 32-BIT MICROPROCESSOR

Intel Corporation
Intel Corporation
80960JA-25

EMBEDDED 32-BIT MICROPROCESSOR

Intel Corporation
Intel Corporation
80960JA-33

EMBEDDED 32-BIT MICROPROCESSOR

Intel Corporation
Intel Corporation
80960JD

EMBEDDED 32-BIT MICROPROCESSOR

Intel Corporation
Intel Corporation


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap