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80188 の電気的特性と機能

80188のメーカーはIntel Corporationです、この部品の機能は「HIGH-INTEGRATION 16-BIT MICROPROCESSORS」です。


製品の詳細 ( Datasheet PDF )

部品番号 80188
部品説明 HIGH-INTEGRATION 16-BIT MICROPROCESSORS
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 




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80188 Datasheet, 80188 PDF,ピン配置, 機能
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80186 80188
HIGH-INTEGRATION 16-BIT MICROPROCESSORS
Y Integrated Feature Set
Enhanced 8086-2 CPU
Clock Generator
2 Independent DMA Channels
Programmable Interrupt Controller
3 Programmable 16-bit Timers
Programmable Memory and
Peripheral Chip-Select Logic
Programmable Wait State Generator
Local Bus Controller
Y Available in 10 MHz and 8 MHz
Versions
Y High-Performance Processor
4 Mbyte Sec Bus Bandwidth
Interface 8 MHz (80186)
5 Mbyte Sec Bus Bandwidth
Interface 10 MHz (80186)
Y Direct Addressing Capability to 1 Mbyte
of Memory and 64 Kbyte I O
Y Completely Object Code Compatible
with All Existing 8086 8088 Software
10 New Instruction Types
Y Numerics Coprocessing Capability
Through 8087 Interface
Y Available in 68 Pin
Plastic Leaded Chip Carrier (PLCC)
Ceramic Pin Grid Array (PGA)
Ceramic Leadless Chip Carrier (LCC)
Y Available in EXPRESS
Standard Temperature with Burn-In
Extended Temperature Range
(b40 C to a85 C)
Figure 1 Block Diagram
272430 – 1
Other brands and names are the property of their respective owners
Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or
copyright for sale and use of Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make
changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
November 1994
Order Number 272430-002
COPYRIGHT INTEL CORPORATION 1995
1
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80188 pdf, ピン配列
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Contacts Facing Up
80186 80188
Contacts Facing Down
Figure 2 Ceramic Leadless Chip Carrier (JEDEC Type A)
Pins Facing Up
Pins Facing Down
272430 – 2
Figure 3 Ceramic Pin Grid Array
NOTE
Pin names in parentheses apply to the 80188
272430 – 3
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80188 電子部品, 半導体
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80186 80188
Table 1 Pin Descriptions (Continued)
Symbol
Pin
No
Type
Name and Function
A19 S6
A18 S5
A17 S4
A16 S3
65 O Address Bus Outputs (16–19) and Bus Cycle Status (3–6) indicate the four most
66 O significant address bits during T1 These signals are active HIGH During T2 T3 TW
67 O and T4 the S6 pin is LOW to indicate a CPU-initiated bus cycle or HIGH to indicate a
68 O DMA-initiated bus cycle During the same T-states S3 S4 and S5 are always LOW
The status pins float during bus HOLD or RESET
AD15 (A15)
AD14 (A14)
AD13 (A13)
AD12 (A12)
AD11 (A11)
AD10 (A10)
AD9 (A9)
AD8 (A8)
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
1
3
5
7
10
12
14
16
2
4
6
8
11
13
15
17
I O Address Data Bus signals constitute the time multiplexed memory or I O address (T1)
I O and data (T2 T3 TW and T4) bus The bus is active HIGH A0 is analogous to BHE for
I O the lower byte of the data bus pins D7 through D0 It is LOW during T1 when a byte is
I O to be transferred onto the lower portion of the bus in memory or I O operations BHE
I O does not exist on the 80188 as the data bus is only 8 bits wide
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BHE S7
(S7)
64 O During T1 the Bus High Enable signal should be used to determine if data is to be
enabled onto the most significant half of the data bus pins D15–D8 BHE is LOW
during T1 for read write and interrupt acknowledge cycles when a byte is to be
transferred on the higher half of the bus The S7 status information is available during
T2 T3 and T4 S7 is logically equivalent to BHE BHE S7 floats during HOLD On the
80188 S7 is high during normal operation
BHE and A0 Encodings (80186 Only)
BHE A0
Value Value
Function
0 0 Word Transfer
0 1 Byte Transfer on upper half of data bus (D15–D8)
1 0 Byte Transfer on lower half of data bus (D7–D0)
1 1 Reserved
ALE QS0 61 O Address Latch Enable Queue Status 0 is provided by the processor to latch the
address ALE is active HIGH Addresses are guaranteed to be valid on the trailing
edge of ALE The ALE rising edge is generated off the rising edge of the CLKOUT
immediately preceding T1 of the associated bus cycle effectively one-half clock cycle
earlier than in the 8086 The trailing edge is generated off the CLKOUT rising edge in
T1 as in the 8086 Note that ALE is never floated
WR QS1
63 O Write Strobe Queue Status 1 indicates that the data on the bus is to be written into a
memory or an I O device WR is active for T2 T3 and TW of any write cycle It is active
LOW and floats during HOLD When the processor is in queue status mode the ALE
QS0 and WR QS1 pins provide information about processor instruction queue
interaction
QS1 QS0
Queue Operation
0 0 No queue operation
0 1 First opcode byte fetched from the queue
1 1 Subsequent byte fetched from the queue
1 0 Empty the queue
NOTE
Pin names in parentheses apply to the 80188
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共有リンク

Link :


部品番号部品説明メーカ
80186

HIGH-INTEGRATION 16-BIT MICROPROCESSORS

Intel Corporation
Intel Corporation
80188

HIGH-INTEGRATION 16-BIT MICROPROCESSORS

Intel Corporation
Intel Corporation
80188

High Integration 16-Bit Microprocessor iAPX86 Family

Advanced Micro Devices
Advanced Micro Devices


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