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7LVC374APWDH の電気的特性と機能

7LVC374APWDHのメーカーはNXP Semiconductorsです、この部品の機能は「Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State」です。


製品の詳細 ( Datasheet PDF )

部品番号 7LVC374APWDH
部品説明 Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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7LVC374APWDH Datasheet, 7LVC374APWDH PDF,ピン配置, 機能
INTEGRATED CIRCUITS
74LVC374A
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger
(3-State)
Product specification
1998 Jul 29
Philips
Semiconductors

1 Page





7LVC374APWDH pdf, ピン配列
Philips Semiconductors
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Product specification
74LVC374A
PIN CONFIGURATION
OE 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SA00389
PIN DESCRIPTION
PIN NUMBER SYMBOL
FUNCTION
1
3, 4, 7, 8, 13,
14, 17, 18
OE
D0-D7
Output enable input (active-Low)
Data inputs
2, 5, 6, 9, 12,
15, 16, 19
11
10
Q0-Q7
CP
GND
3-state flip-flop outputs
Clock input (LOW-to-HIGH,
edge-triggered)
Ground (0V)
20 VCC Positive supply voltage
LOGIC SYMBOL
11
3
D0 CP
Q0
4 D1
Q1
7 D2
Q2
8 D3
13 D4
Q3
Q4
14 D5
Q5
17 D6
Q6
18 D7 OE Q7
2
5
6
9
12
15
16
19
1
SA00390
LOGIC SYMBOL (IEEE/IEC)
11
C1
1 EN1
3 1D
4
7
8
13
14
17
18
2
5
6
9
12
15
16
19
SA00391
FUNCTIONAL DIAGRAM
3 D0
4 D1
7 D2
8 D3
13 D4
14 D5
17 D6
18 D7
11 CP
1 OE
FF1
to
FF8
Q0
Q1
Q2
3-State
OUTPUTS
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
SA00392
1998 Jul 29
3


3Pages


7LVC374APWDH 電子部品, 半導体
Philips Semiconductors
Octal D-type flip-flop with 5-volt tolerant
inputs/outputs; positive edge-trigger (3-State)
Product specification
74LVC374A
DC ELECTRICAL CHARACTERISTICS
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Temp = -40°C to +85°C
MIN TYP1 MAX
VIH HIGH level Input voltage
VCC = 1.2V
VCC = 2.7 to 3.6V
VCC
2.0
VIL LOW level Input voltage
VCC = 1.2V
VCC = 2.7 to 3.6V
VCC = 2.7V; VI = VIH or VIL; IO = –12mA
VCC*0.5
VOH HIGH level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = –100µA
VCC = 3.0V; VI = VIH or VIL; IO = –18mA
VCC*0.2
VCC*0.6
VCC = 3.0V; VI = VIH or VIL; IO = –24mA
VCC*0.8
VCC = 2.7V; VI = VIH or VIL; IO = 12mA
VOL LOW level output voltage
VCC = 3.0V; VI = VIH or VIL; IO = 100µA
VCC = 3.0V; VI = VIH or VIL; IO = 24mA
II Input leakage current2
VCC = 3.6V; VI = 5.5V or GND
IOZ 3-State output OFF-state current
VCC = 3.6V; VI = VIH or VIL; VO = 5.5V or GND
Ioff Power off leakage supply
VCC = 0.0V; VI or VO = 5.5V
ICC Quiescent supply current
VCC = 3.6V; VI = VCC or GND; IO = 0
ICC
Additional quiescent supply current
per input pin
VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0
NOTES:
1. All typical values are at VCC = 3.3V and Tamb = 25°C.
2. The specified overdrive current at the data input forces the data input to the opposite logic input state.
VCC
GND
"0.1
0.1
0.1
0.1
5
GND
0.8
0.40
0.20
0.55
"5
"10
"10
10
500
UNIT
V
V
V
V
µA
µA
µA
µA
µA
AC CHARACTERISTICS
GND = 0V; tr = tf v 2.5ns; CL = 50pF; RL = 500; Tamb = –40°C to +85°C.
SYMBOL
PARAMETER
WAVEFORM
VCC = 3.3V ±0.3V
MIN TYP1 MAX
tPHL
tPLH
tPZH
tPZL
tPHZ
tPLZ
Propagation delay
CP to Qn
3-State output enable time
OE to Qn
3-State output disable time
OE to Qn
1, 4 1.5 4.8 7.0
2, 4 1.5 4.8 7.5
2, 4 1.5 4.3 6.0
tW Clock pulse width HIGH or LOW
1
3.0 1.5
tSU
Setup time
Dn to CP
3 2.0 0
th
Hold time
Dn to CP
3 1.5 0.6
fmax maximum clock pulse frequency
1
100 –
NOTE:
1. Unless otherwise stated, all typical values are at VCC = 3.3V and Tamb = 25°C.
LIMITS
VCC = 2.7V
MIN MAX
1.5 8.0
1.5 8.5
1.5 7.0
3.0 –
2.0 –
1.5 –
80 –
VCC = 1.2V
TYP
21
22
15
UNIT
ns
ns
ns
ns
ns
ns
MHz
1998 Jul 29
6

6 Page



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部品番号部品説明メーカ
7LVC374APWDH

Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger 3-State

NXP Semiconductors
NXP Semiconductors


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