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74VCX162373のメーカーはFairchild Semiconductorです、この部品の機能は「Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs」です。 |
部品番号 | 74VCX162373 |
| |
部品説明 | Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs | ||
メーカ | Fairchild Semiconductor | ||
ロゴ | |||
このページの下部にプレビューと74VCX162373ダウンロード(pdfファイル)リンクがあります。 Total 7 pages
January 2000
Revised January 2000
74VCX162373
Low Voltage 16-Bit Transparent Latch
with 3.6V Tolerant Inputs and Outputs
and 26Ω Series Resistors in Outputs
General Description
The VCX162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear to be transparent to the data when the Latch enable
(LE) is HIGH. When LE is LOW, the data that meets the
setup time is latched. Data appears on the bus when the
Output Enable (OE) is LOW. When OE is HIGH, the out-
puts are in a high impedance state.
The VCX162373 is also designed with 26Ω resistors in the
outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers and bus
transceivers/transmitters.
The 74VCX162373 is designed for low voltage (1.65V to
3.6V) VCC applications with I/O compatibility up to 3.6V.
The 74VCX162373 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.65V–3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26Ω series resistors in outputs
s tPD (In to On)
3.3 ns max for 3.0V to 3.6V VCC
4.5 ns max for 2.3V to 2.7V VCC
9.0 ns max for 1.65V to 1.95V VCC
s Power-off high impedance inputs and outputs
s Support live insertion and withdrawal (Note 1)
s Static Drive (IOH/IOL)
±12 mA @ 3.0V VCC
±8 mA @ 2.3V VCC
±3 mA @ 1.65V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model > 2000V
Machine model > 200V
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Ordering Number
Package
Number
Package Description
74VCX162373MTD
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OEn
LEn
I0–I15
O0–O15
Description
Output Enable Input (Active LOW)
Latch Enable Input
Inputs
Outputs
© 2000 Fairchild Semiconductor Corporation DS500236
www.fairchildsemi.com
1 Page Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
DC Input Voltage (VI)
Output Voltage (VO)
Outputs 3-STATED
Outputs Active (Note 3)
DC Input Diode Current (IIK)
VI < 0V
DC Output Diode Current (IOK)
VO < 0V
VO > VCC
DC Output Source/Sink Current
(IOH/IOL)
DC VCC or GND Current per
Supply Pin (ICC or GND)
Storage Temperature Range (TSTG)
−0.5V to +4.6V
−0.5V to +4.6V
−0.5V to +4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
+50 mA
±50 mA
±100 mA
−65°C to +150°C
Recommended Operating
Conditions (Note 4)
Power Supply
Operating
1.65V to 3.6V
Data Retention Only
1.2V to 3.6V
Input Voltage
−0.3V to +3.6V
Output Voltage (VO)
Output in Active States
Output in “OFF” State
0V to VCC
0.0V to 3.6V
Output Current in IOH/IOL
VCC = 3.0V to 3.6V
VCC = 2.3V to 2.7V
VCC = 1.65V to 2.3V
Free Air Operating Temperature (TA)
Minimum Input Edge Rate (∆t/∆V)
±12 mA
±8 mA
±3 mA
−40°C to +85°C
VIN = 0.8V to 2.0V, VCC = 3.0V
10 ns/V
Note 2: The Absolute Maximum Ratings are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the Absolute Maximum Rat-
ings. The “Recommended Operating Conditions” table will define the condi-
tions for actual device operation.
Note 3: IO Absolute Maximum Rating must be observed.
Note 4: Floating or unused inputs must be held HIGH or LOW.
DC Electrical Characteristics (2.7V < VCC ≤ 3.6V)
Symbol
Parameter
VIH HIGH Level Input Voltage
VIL LOW Level Input Voltage
VOH HIGH Level Output Voltage
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power-OFF Leakage Current
ICC Quiescent Supply Current
∆ICC
Increase in ICC per Input
Note 5: Outputs disabled or 3-STATE only.
Conditions
IOH = −100 µA
IOH = −6 mA
IOH = −8 mA
IOH = −12 mA
IOL = 100 µA
IOL = 6 mA
IOL = 8 mA
IOL = 12 mA
0 ≤ VI ≤ 3.6V
0 ≤ VO ≤ 3.6V
VI = VIH or VIL
0 ≤ (VI, VO) ≤ 3.6V
VI = VCC or GND
VCC ≤ (VI, VO) ≤ 3.6V (Note 5)
VIH = VCC −0.6V
VCC
(V)
2.7–3.6
2.7–3.6
2.7–3.6
2.7
3.0
3.0
2.7–3.6
2.7
3.0
3.0
2.7–3.6
Min
2.0
VCC − 0.2
2.2
2.4
2.2
2.7–3.6
0
2.7–3.6
2.7–3.6
2.7–3.6
Max
0.8
0.2
0.4
0.55
0.8
±5.0
±10
10
20
±20
750
Units
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
3 www.fairchildsemi.com
3Pages AC Loading and Waveforms
TEST
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
SWITCH
Open
6V at VCC = 3.3 ± 0.3V;
VCC x 2 at VCC = 2.5 ± 0.2V; 1.8V ± 0.15V
GND
FIGURE 1. AC Test Circuit
FIGURE 2. Waveform for Inverting and
Non-Inverting Functions
FIGURE 3. 3-STATE Output HIGH Enable and
Disable Times for Low Voltage Logic
FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic
FIGURE 5. Propagation Delay, Pulse Width and
tREC Waveforms
Symbol
Vmi
Vmo
VX
VY
3.3V ± 0.3V
1.5V
1.5V
VOL +0.3V
VOH −0.3V
FIGURE 6. Setup Time, Hold Time and
Recovery Time for Low Voltage Logic
VCC
2.5V ± 0.2V
VCC/2
VCC/2
VOL +0.15V
VOH −0.15V
1.8V ± 0.15V
VCC/2
VCC/2
VOL +0.15V
VOH −0.15V
www.fairchildsemi.com
6
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部品番号 | 部品説明 | メーカ |
74VCX162373 | Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs | Fairchild Semiconductor |
74VCX162374 | Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs and 26 Series Resistors in Outputs | Fairchild Semiconductor |