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PDF 74VCX162244 Data sheet ( Hoja de datos )
| Número de pieza | 74VCX162244 | |
| Descripción | Low Voltage 16-Bit Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26 Series Resistor in Outputs | |
| Fabricantes | Fairchild Semiconductor | |
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August 1997
Revised June 2005
74VCX162244
Low Voltage 16-Bit Buffer/Line Driver
with 3.6V Tolerant Inputs and Outputs
and 26: Series Resistor in Outputs
General Description
The VCX162244 contains sixteen non-inverting buffers
with 3-STATE outputs to be employed as a memory and
address driver, clock driver, or bus oriented transmitter/
receiver. The device is nibble (4-bit) controlled. Each nibble
has separate 3-STATE control inputs which can be shorted
together for full 16-bit operation.
The 74VCX162244 is designed for low voltage (1.2V to
3.6V) VCC applications with I/O capability up to 3.6V. The
74VCX162244 is also designed with 26: series resistors in
the outputs. This design reduces line noise in applications
such as memory address drivers, clock drivers, and bus
transceivers/transmitters.
The 74VCX162244 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s 1.2V to 3.6V VCC supply operation
s 3.6V tolerant inputs and outputs
s 26: series resistors in outputs
s tPD
3.3 ns max for 3.0V to 3.6V VCC
s Power-off high impedance inputs and outputs
s Supports live insertion and withdrawal
s Static Drive (IOH/IOL)
r12 mA @ 3.0V VCC
s Uses patented noise/EMI reduction circuitry
s Latch-up performance exceeds 300 mA
s ESD performance:
Human body model ! 2000V
Machine model ! 200V
s Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA)
Note 1: To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number Package Number
Package Description
74VCX162244G
(Note 2)(Note 3)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74VCX162244MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: Ordering Code “G” indicates Trays.
Note 3: Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Logic Symbol
© 2005 Fairchild Semiconductor Corporation DS500040
www.fairchildsemi.com
1 page  
DC Electrical Characteristics (2.7V < VCC £ 3.6V) (Continued)
Symbol
Parameter
VOL LOW Level Output Voltage
II Input Leakage Current
IOZ 3-STATE Output Leakage
IOFF Power-OFF Leakage Current
ICC Quiescent Supply Current
'ICC
Increase in ICC per Input
Note 7: Outputs disabled or 3-STATE only.
Conditions
IOL 100 PA
IOL 6 mA
IOL 8 mA
IOL 12 mA
IOL 100 PA
IOL 6 mA
IOL 8 mA
IOL 100 PA
IOL 3 mA
IOL 100 PA
IOL 1 mA
IOL 100 PA
0 d VI d 3.6V
0 d VO d 3.6V
VI VIH or VIL
0 d (VI, VO) d 3.6V
VI VCC or GND
VCC d (VI, VO) d 3.6V (Note 7)
VIH VCC 0.6V
VCC
(V)
2.7 - 3.6
2.7
3.0
3.0
2.7 - 3.6
2.3
2.3
1.65 - 2.3
1.65
1.4 - 1.6
1.4
1.2
1.2 - 3.6
1.2 - 3.6
0
1.2 - 3.6
1.2 - 3.6
2.7 - 3.6
Min
Max
Units
0.2
0.4
0.55
0.8
0.2
0.4
V
0.6
0.2
0.3
0.2
0.35
0.1
r5.0 PA
r10 PA
10
PA
20
r20 PA
750 PA
AC Electrical Characteristics (Note 8)
Symbol
Parameter
Conditions
VCC
TA 40qC to 85qC
Units
Figure
(V) Min Max
Number
tPHL,
tPLH
Propagation Delay
CL 30 pF, RL 500:
3.3 r 0.3
2.5 r 0.2
0.8
1.0
3.3
3.8
Figures
1, 2
1.8 r 0.15
1.5
7.6
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.2
1.0
1.5
15.2
38
Figures
5, 6
tPZL,
tPZH
Output Enable Time
CL 30 pF, RL 500:
3.3 r 0.3
0.8
3.8
2.5 r 0.2
1.0
5.1
Figures
1, 3, 4
1.8 r 0.15
1.5
9.8
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.2
1.0
1.5
19.6
49
Figures
5, 7, 8
tPLZ,
tPHZ
Output Disable Time
CL 30 pF, RL 500:
3.3 r 0.3
0.8
3.6
2.5 r 0.2
1.0
4.0
Figures
1, 3, 4
1.8 r 0.15
1.5
7.2
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.2
1.0
1.5
14.4
36
Figures
5, 7, 8
tOSHL
tOSLH
Output to Output Skew
(Note 9)
CL 30 pF, RL 500:
3.3 r 0.3
2.5 r 0.2
1.8 r 0.15
0.5
0.5
0.75
ns
CL 15 pF, RL 2k:
1.5 r 0.1
1.2
1.5
1.5
Note 8: For CL 50 PF, add approximately 300 ps to the AC maximum specification.
Note 9: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
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| PDF Descargar | [ Datasheet 74VCX162244.PDF ] | |
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