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74V1T00 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 74V1T00
部品説明 SINGLE 2-INPUT NAND GATE
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 

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74V1T00 Datasheet, 74V1T00 PDF,ピン配置, 機能
® 74V1T00
SINGLE 2-INPUT NAND GATE
s HIGH SPEED: tPD = 5 ns (TYP.) at VCC = 5V
s LOW POWER DISSIPATION:
ICC = 1 µA (MAX.) at TA = 25 oC
s COMPATIBLE WITH TTL OUTPUTS:
VIH = 2V (MIN), VIL = 0.8V (MAX)
s POWER DOWN PROTECTION ON INPUTS &
OUTPUT
s SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
s BALANCED PROPAGATION DELAYS:
tPLH tPHL
s OPERATING VOLTAGE RANGE:
VCC (OPR) = 4.5V to 5.5V
s IMPROVED LATCH-UP IMMUNITY
DESCRIPTION
The 74V1T00 is an advanced high-speed CMOS
SINGLE 2-INPUT NAND GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
S
(SOT23-5L)
C
(SC-70)
ORDER CODE:
74V1T00S
74V1T00C
The internal circuit is composed of 3 stages
including buffer output, which provide high noise
immunity and stable output.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
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