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MAX5309 の電気的特性と機能

MAX5309のメーカーはMaxim Integratedです、この部品の機能は「PLASTIC ENCAPSULATED DEVICES」です。


製品の詳細 ( Datasheet PDF )

部品番号 MAX5309
部品説明 PLASTIC ENCAPSULATED DEVICES
メーカ Maxim Integrated
ロゴ Maxim Integrated ロゴ 




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MAX5309 Datasheet, MAX5309 PDF,ピン配置, 機能
MAX5309EUE
Rev. A
RELIABILITY REPORT
FOR
MAX5309EUE
PLASTIC ENCAPSULATED DEVICES
March 30, 2004
MAXIM INTEGRATED PRODUCTS
120 SAN GABRIEL DR.
SUNNYVALE, CA 94086
Written by
Jim Pedicord
Quality Assurance
Reliability Lab Manager
Reviewed by
Bryan J. Preeshl
Quality Assurance
Executive Director

1 Page





MAX5309 pdf, ピン配列
II. Manufacturing Information
A. Description/Function:
Low-Power, Low-Glitch, Octal 10-Bit Voltage-Output DACs with Serial Interface
B. Process:
S6 (Standard 0.6 micron silicon gate CMOS)
C. Number of Device Transistors:
19,000
D. Fabrication Location:
California, USA
E. Assembly Location:
F. Date of Initial Production:
Malaysia or Thailand
July, 2001
III. Packaging Information
A. Package Type:
16-Pin TSSOP
B. Lead Frame:
Copper
C. Lead Finish:
Solder Plate
D. Die Attach:
Silver-Filled Epoxy
E. Bondwire:
Gold (1 mil dia.)
F. Mold Material:
Epoxy with silica filler
G. Assembly Diagram:
#05-3901-0002
H. Flammability Rating:
Class UL94-V0
I. Classification of Moisture Sensitivity
per JEDEC standard J-STD-020-A: Level 1
IV. Die Information
A. Dimensions:
B. Passivation:
C. Interconnect:
D. Backside Metallization:
E. Minimum Metal Width:
F. Minimum Metal Spacing:
G. Bondpad Dimensions:
H. Isolation Dielectric:
I. Die Separation Method:
102 x 141 mils
Si3N4/SiO2 (Silicon nitride/ Silicon dioxide)
Aluminum/Si (Si = 1%)
None
0.6 microns (as drawn)
0.6 microns (as drawn)
5 mil. Sq.
SiO2
Wafer Saw


3Pages


MAX5309 電子部品, 半導体
Attachment #1
TABLE II. Pin combination to be tested. 1/ 2/
Terminal A
(Each pin individually
connected to terminal A
with the other floating)
Terminal B
(The common combination
of all like-named pins
connected to terminal B)
1. All pins except VPS1 3/
All VPS1 pins
2.
All input and output pins
All other input-output pins
1/ Table II is restated in narrative form in 3.4 below.
2/ No connects are not to be tested.
3/ Repeat pin combination I for each named Power supply and for ground
(e.g., where VPS1 is VDD, VCC, VSS, VBB, GND, +VS, -VS, VREF, etc).
3.4 Pin combinations to be tested.
a. Each pin individually connected to terminal A with respect to the device ground pin(s) connected
to terminal B. All pins except the one being tested and the ground pin(s) shall be open.
b. Each pin individually connected to terminal A with respect to each different set of a combination
of all named power supply pins (e.g., VSS1, or VSS2 or VSS3 or VCC1, or VCC2) connected to
terminal B. All pins except the one being tested and the power supply pin or set of pins shall be
open.
c. Each input and each output individually connected to terminal A with respect to a combination of
all the other input and output pins connected to terminal B. All pins except the input or output pin
being tested and the combination of all the other input and output pins shall be open.
R1
REGULATED
HIGH VOLTAGE
SUPPLY
Mil Std 883D
Method 3015.7
Notice 8
TERMINAL C
R2
S1
TERMINAL A
S2 DUT
SHORT
C1 SOCKET
CURRENT
TERMINAL B
PROBE
(NOTE 6)
TERMINAL D
R = 1.5k
C = 100pf

6 Page



ページ 合計 : 8 ページ
 
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[ MAX5309 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


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