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PI6C3991J の電気的特性と機能

PI6C3991JのメーカーはETCです、この部品の機能は「3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C3991J
部品説明 3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock
メーカ ETC
ロゴ ETC ロゴ 




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PI6C3991J Datasheet, PI6C3991J PDF,ピン配置, 機能
PI6C39911122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock®
Features
• All output pair skew <100ps typical (250 Max.)
• 3.75 MHz to 80 MHz output operation
• User-selectable output functions
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— Selectable skew to 18ns
— Inverted and Non-Inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50-ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• Available in 32-pin PLCC (J) package
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Logic Block Diagram
Description
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Pin Configuration
Test
FB
REF
Phase
Freq.
DET
Filter
FS
4F0
4F1
Select Inputs
(three level)
3F0
3F1
2F0
2F1
1F0
1F1
VCO and
Time Unit
Generator
Skew
Select
Matrix
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7 27
8
32-Pin
26
9 25
J10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
1 PS8450B 04/09/01

1 Page





PI6C3991J pdf, ピン配列
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122S1122k3344e55w667788C9900l11o2233c44k5566B7788u9900f11f22e3344r5566-77S8899u0011p22e1122r33C4455l66o77c8899k00®1122
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept input signals from the reference frequency
(REF) input and the feedback (FB) input and generate correction
information to control the frequency of the Voltage-Controlled
Oscillator (VCO). These blocks, along with the VCO, form a Phase-
Locked Loop (PLL) that tracks the incoming REF signal.
VCO and Time Unit Generator
www.DataSThheeetV4UC.Ocomaccepts analog control inputs from the PLL filter block
and generates a frequency that is used by the time unit generator
to create discrete time units that are selected in the skew mix matrix.
The operational range of the VCO is determined by the FS control
pin. The time unit (tU) is determined by the operating frequency of
the device and the level of the FS pin as shown in Table 1.
Skew Select Matrix
The skew select matrix is comprised of four independent sections.
Each section has two low-skew, high-fanout drivers (xQ0, xQ1),
and two corresponding three-level function select (xF0, xF1)
inputs. Table 2 shows the nine possible output functions for each
section as determined by the function select inputs. All times are
measured with respect to the REF input assuming that the output
connected to the FB input has 0tU selected.
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C3991 to operate
as explained briefly above (for testing purposes, any of the three
level inputs can have a removable jumper to ground, or be tied LOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and input
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of
the REF input.
Maximum Ratings
Storage Temperature ...................................... –65°C to +150°C
Ambient Temperature with
Power Applied ................................................. –55°Cto+125°C
Supply Voltage to Ground Potential .................. –0.5V to +7.0V
DC Input Voltage ............................................... –0.5Vto+7.0V
Output Current into Outputs (LOW) ............................... 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................... >200mA
FB Input
REF Input
1Fx 3Fx
2Fx 4Fx
(N/A) LM –6tU
LL LH –4tU
LM (N/A) –3tU
LH ML –2tU
ML (N/A) –1tU
MM MM 0tU
MH (N/A) +1tU
HL MH +2tU
HM (N/A) +3tU
HH HL +4tU
(N/A) HM +6tU
(N/A) LL/HH Divided
(N/A) HH Invert
Figure 1. Typical Outputs with FB Connected to a
Zero-Skew Output(3)
Operating Range
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VCC
3.3V ±10%
3.3V ±10%
Note:
3. FB connected to an output selected for "zero" skew
(ie., xF1 = xF0 = MID).
3 PS8450B 04/09/01


3Pages


PI6C3991J 電子部品, 半導体
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122S1122k3344e55w667788C9900l11o2233c44k5566B7788u9900f11f22e3344r5566-77S8899u0011p22e1122r33C4455l66o77c8899k00®1122
AC Test Loads and Waveforms
TTL AC Test Load
VCC
R1
www.DataSheet4U.com
CL
R2
R1=100
R2=100
CL=30pF
(Includes fixture and probe capacitance)
TTL Input Test Waveform
3.0V
2.0V
Vth=1.5V
0.8V
0V
1ns
1ns
AC Timing Diagrams
REF
tPD
FB
Q
Other Q
Inverted Q
REF Divided by 2
REF Divided by 4
tREF
tRPWH
tRPWL
tODCV tODCV
ttSSKKEEWW0P,R1
tSKEW3,4
tSKEW1,3,4
ttSSKKEEWW0P,R1
tSKEW2
tSKEW3,4
tJR
tSKEW2
tSKEW3,4
tSKEW2,4
6 PS8450B 04/09/01

6 Page



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共有リンク

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部品番号部品説明メーカ
PI6C3991

3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock

ETC
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3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock

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PI6C3991-5IJ

3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock

ETC
ETC
PI6C3991-5J

3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock

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