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PI6C39911-2J の電気的特性と機能

PI6C39911-2JのメーカーはPericom Semiconductor Corporationです、この部品の機能は「3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C39911-2J
部品説明 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock
メーカ Pericom Semiconductor Corporation
ロゴ Pericom Semiconductor Corporation ロゴ 




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PI6C39911-2J Datasheet, PI6C39911-2J PDF,ピン配置, 機能
PI6C399111122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer - SuperClock®
Features
• All output pair skew <100ps typical (250 Max.)
• 12.5 MHz to 133 MHz output operation
• 3.125 MHz to 133 MHz input operation (input as low as 3.125
MHz for 4x operation, or 6.25 MHz for 2x operation)
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
• Zero input-to-output delay
• 50% duty-cycle outputs
• Inputs are 5V Tolerant
• LVTTL outputs drive 50-Ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
Test
FB
REF
FS
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
4F0
4F1
3F0
3F1
Select Inputs
(three level)
2F0
2F1
Skew
Select
Matrix
1F0
1F1
Pin Configuration
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7
8 32 Pin
9J
27
26
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
1
PS8497E
09/13/02

1 Page





PI6C39911-2J pdf, ピン配列
PI6C39911
3.3V High Speed LVTTL or Balanced Output
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122P3344r5566o77g8899r00a1122m3344m556677a88b9900l11e2211S2233k44e5566w778899C0011l22o33c4455k6677B8899u0011f22f33e44r5566-7788S99u0011p2211e22r33C4455l66o7788c99k001122
Test Mode
The TEST input is a three-level input. In normal system operation,
this pin is connected to ground, allowing the PI6C39911 to operate
as explained briefly above (for testing purposes, any of the three
level inputs can have a removable jumper to ground, or be tied LOW
through a 100 Ohm resistor. This will allow an external tester to
change the state of these pins.)
If the TEST input is forced to its MID or HIGH state, the device will
operate with its internal phase locked loop disconnected, and input
levels supplied to REF will directly control all outputs. Relative
output to output functions are the same as in normal mode.
In contrast with normal operation (TEST tied LOW). All outputs
will function based only on the connection of their own function
select inputs (xF0 and xF1) and the waveform characteristics of the
REF input.
Maximum Ratings
Storage Temperature ..................................... –65°C to +150°C
Ambient Temperature with
Power Applied ............................................... –55°C to +125°C
Supply Voltage to Ground Potential ................ –0.5V to +5.0V
DC Input Voltage .............................................. –0.5Vto+5.0V
Output Current into Outputs (LOW) .............................. 64mA
Static Discharge Voltage ............................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current ......................................................... >200mA
Maximum Power Dissipation at TA=85°C(2,3) .............. 0.80watts
Operating Range
Range
Ambient Temperature
Commercial
0°C to +70°C
Industrial
–40°C to +85°C
VCC
3.3V ±10%
3.3V ±10%
FB Input
REF Input
1Fx 3Fx
2Fx 4Fx
(N/A) LM –6tU
LL LH –4tU
LM (N/A) –3tU
LH ML –2tU
ML (N/A) –1tU
MM MM
0tU
MH (N/A) +1tU
HL MH +2tU
HM (N/A) +3tU
HH HL +4tU
(N/A) HM +6tU
(N/A) LL/HH Divided
(N/A) HH Invert
Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output(3)
Note:
3. FB connected to an output selected for “zero” skew (i.e., xF1 = xF0 = MID)
3
PS8497E
09/13/02


3Pages


PI6C39911-2J 電子部品, 半導体
PI6C39911
3.3V High Speed LVTTL or Balanced Output
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122P3344r55o6677g88r9900a11m223344m556677a88b9900l11e2211S22k3344e55w667788C990011lo2233c44k556677B8899u0011f22f33e44r5566-7788S99u0011p2211e22r33C4455l66o7788c99k001122
AC Test Loads and Waveforms
TTL AC Test Load
VCC
TTL Input Test Waveform
R1
CL R2
R1=100
R2=100
CL=30pF (Includes fixture and probe capacitance)
3.0V
2.0V
Vth =1.5V
0.8V
0V
1ns
1ns
AC Timing Diagrams
REF
tPD
FB
Q
Other Q
Inverted Q
REF Divided by 2
REF Divided by 4
tREF
tRPWH
tRPWL
tODCV tODCV
ttSSKKEEWW0P,R1
tSKEW3,4
tSKEW1,3,4
ttSSKKEEWW0P,R1
tSKEW2
tSKEW3,4
tJR
tSKEW2
tSKEW3,4
tSKEW2,4
6
PS8497E
09/13/02

6 Page



ページ 合計 : 11 ページ
 
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部品番号部品説明メーカ
PI6C39911-2J

3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock

Pericom Semiconductor Corporation
Pericom Semiconductor Corporation


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