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PDF PI6C39911 Data sheet ( Hoja de datos )
| Número de pieza | PI6C39911 | |
| Descripción | 3.3V High Speed LVTTL or Balanced Output Programmable Skew Clock Buffer - SuperClock | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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PI6C399111122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer - SuperClock®
Features
• All output pair skew <100ps typical (250 Max.)
• 12.5 MHz to 133 MHz output operation
• 3.125 MHz to 133 MHz input operation (input as low as 3.125
MHz for 4x operation, or 6.25 MHz for 2x operation)
• User-selectable output functions
— Selectable skew to 18ns
— Inverted and non-inverted
— Operation at ½ and ¼ input frequency
— Operation at 2X and 4X input frequency
• Zero input-to-output delay
• 50% duty-cycle outputs
• Inputs are 5V Tolerant
• LVTTL outputs drive 50-Ohm terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter < 200ps peak-to-peak (< 25ps RMS)
Description
The PI6C39911 offers selectable control over system clock func-
tions. These multiple-output clock drivers provide the system
integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50-Ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal “zero” skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
Test
FB
REF
FS
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
4F0
4F1
3F0
3F1
Select Inputs
(three level)
2F0
2F1
Skew
Select
Matrix
1F0
1F1
Pin Configuration
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7
8 32 Pin
9J
27
26
25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
1
PS8497E
09/13/02
1 page  
PI6C39911
3.3V High Speed LVTTL or Balanced Output
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122P3344r5566o77g8899r00a1122m3344m556677a88b9900l11e2211S2233k44e5566w778899C0011l22o33c4455k6677B8899u0011f22f33e44r5566-7788S99u0011p2211e22r33C4455l66o7788c99k001122
Switching Characteristics (Over the Operating Range)(2,7)
Parame te r
D e s cription
fN O M(1,2)
tRP W H
tRP W L
tU
tS K EW P R
tS K EW 0
tS K EW 1
tS K EW 2
tS K EW 3
tS K EW 4
tDEV
tPD
tO DC V
tP W H
tP W L
tO RIS E
tO FALL
tLO C K
tJR
Operating
Clock
Frequency
in MHz
FS = LOW(1,2)
FS = MID(1,2)
FS = HIGH(1,2)
REF Pulse Width HIGH
REF Pulse Width LOW
Programmable Skew Unit
Zero Output Matched
-Pair Skew (XQ0, XQ1)(9,10)
Zero Output Skew (All Outputs)(9,11)
Output Skew (Rise-Rise, Fall-Fall,
Same Class Outputs)(9,13)
Output Skew (Rise-Fall, Nominal-Inverted,
Divided- Divided)(9 , 1 3 )
Output Skew (Rise-Rise, Fall-Fall,
Different Class Outputs)(9,13)
Output Skew (Rise-Fall, Nominal-Divided,
Divided- Inverted)(9 , 1 3 )
Device-to-Device Skew (8,14)
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation (15)
Output HIGH Time Deviation from 50%(16)
Output LOW Time Deviation from 50%(16)
Output Rise Time(16,17)
Output Fall Time(16,17)
PLL Lock Time(18)
C ycle- to- cycle
Output Jitter
RMS(8)
Peak- to- peak(8 )
PI6C39911-2
Min. Typ. Max.
12.5 30
25 50
40 133
3.0
3.0
See Table 1
0.1 0.25
0.20 0.25
0.4 0.5
0.6 0.8
0.4 0.5
0.5 0.8
1.0
–0.3 0.0 +0.3
–1.0 0.0 +1.0
2.5
3.0
0.15 1.0 1.5
0.15 1.0 1.5
0.5
25
200
PI6C39911-5
Min. Typ. Max.
12.5 30
25 50
40 133
3.0
3.0
See Table 1
0.1 0.25
0.25 0.5
0.6 0.7
0.5 1.0
0.5 0.7
0.5 1.0
1.25
–0.5 0.0 +0.5
–1.0 0.0 +1.0
2.5
3.0
0.15 1.0 1.5
0.15 1.0 1.5
0.5
25
200
PI6C39911
Unit-
Min. Typ. Max. s
12.5 30
25 50 MHz
40 133
3.0
3.0 ns
See Table 1
0.1 0.25
0.3 0.75
0.6 1.0
1.0 1.5
0.7 1.2
1.2 1.7 ns
1.65
–0.7 0.0 +0.7
–1.2 0.0 +1.2
3.0
3.5
0.15 1.0 1.5
0.15 1.0 1.5
0.5 ms
25
200 ps
Notes:
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been
selected when all are loaded with 30pF and terminated with 50 ohms to VCC/2.
10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns.
13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided (3Qx
and 4Qx only in Divide-by-2 or Divide-by-4 mode).
14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.)
15. tODCV isthedeviationoftheoutputfroma50%dutycycle.OutputpulsewidthvariationsareincludedintSKEW2 andtSKEW4 specifications.
16. Specified with outputs loaded with 30pF for the PI6C39911 devices. Devices are terminated through 50 Ohm to VCC/2. tPWH is measured
at 2.0V. tPWL is measured at 0.8V.
17. tORISE and tOFALL measured between 0.8V and 2.0V.
18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal
operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
5
PS8497E
09/13/02
5 Page 
PI6C39911
3.3V High Speed LVTTL or Balanced Output
11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122P3344r5566o77g8899r00a1122m3344m556677a88b9900l11e2211S2233k44e5566w778899C0011l22o33c4455k6677B8899u0011f22f33e44r5566-7788S99u0011p2211e22r33C4455l66o7788c99k001122
Packaging Mechanical: 32-Pin PLCC (J32)
Ordering Information
Accuracy (ps)
Ordering Code
250 PI6C39911-2J
500 PI6C39911-5J
750 PI6C39911J
Package
Name
J32
Package Type Operating Range
32-Pin Plastic
Leaded Chip
Carrier
Commercial
Theta JA (in
still air)
(degrees
C/Watt)
52
Theta JC
(degrees C/Watt)
23
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
11
PS8497E
09/13/02
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet PI6C39911.PDF ] | |
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