|
|
PDF PI6C3991-5IJ Data sheet ( Hoja de datos )
| Número de pieza | PI6C3991-5IJ | |
| Descripción | 3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock | |
| Fabricantes | ETC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PI6C3991-5IJ (archivo pdf) en la parte inferior de esta página. Total 11 Páginas | ||
|
No Preview Available !
PI6C39911122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V High-Speed, Low-Voltage
Programmable Skew Clock Buffer
SuperClock®
Features
All output pair skew <100ps typical (250 Max.)
3.75 MHz to 80 MHz output operation
User-selectable output functions
www.DataSheet4U.com
Selectable skew to 18ns
Inverted and Non-Inverted
Operation at ½ and ¼ input frequency
Operation at 2X and 4X input frequency
(input as low as 3.75 MHz, x4 operation)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50-ohm terminated lines
Operates from a single 3.3V supply
Low operating current
Available in 32-pin PLCC (J) package
Jitter < 200ps peak-to-peak (< 25ps RMS)
Logic Block Diagram
Description
PI6C3991 offers selectable control over system clock functions.
These multiple-output clock drivers provide the system integrator
with functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated trans-
mission lines with impedances as low as 50 ohms while delivering
minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow
distribution of a low-frequency clock that can be multiplied by
two or four at the clock destination. This feature allows flexibility
and simplifies system timing distribution design for complex
high-speed systems.
Pin Configuration
Test
FB
REF
Phase
Freq.
DET
Filter
FS
4F0
4F1
Select Inputs
(three level)
3F0
3F1
2F0
2F1
1F0
1F1
VCO and
Time Unit
Generator
Skew
Select
Matrix
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5 29
6 28
7 27
8
32-Pin
26
9 25
J10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
1 PS8450B 04/09/01
1 page  
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122S1122k3344e55w667788C9900l11o2233c44k5566B7788u9900f11f22e3344r5566-77S8899u0011p22e1122r33C4455l66o77c8899k00®1122
Switching Characteristics PI6C3991 (Over the Operating Range)(2,7)
Parameter
fNOM
Operating
Clock Frequency
in MHz
Description
FS = LOW (1,2)
FS = MID (1,2)
FS = HIGH (1,2)
PI6C3991-2
Min. Typ. Max.
15 30
25 50
40 80
tRPWH REF Pulse Width HIGH
tRPWL REF Pulse Width LOW
tU Programmable Skew Unit
www.DataShetSeKtE4WUP.cRomZero Output Matched-Pair Skew (XQ0, XQ1) (9,10)
tSKEW0 Zero Output Skew (All Outputs) (9,11)
tSKEW1 Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) (9,13)
tSKEW2 Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)(9,13)
tSKEW3 Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)(9,13)
tSKEW4 Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted(9,13)
tDEV Device-to-Device Dkew(8,14)
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
tJR
Propagation Delay, REF Rise to FB Rise
Output Duty Cycle Variation(15)
Output HIGH Time Deviation from 50% (16)
Output LOW Time Deviation from 50%(16)
Output Rise Time(16,17)
Output Fall Time(16,17)
PLL Lock Time(18)
Cycle-to-cycle
Output Jitter
RMS(8)
Peak-to-peak(8)
5.0
5.0
See Table 1
0.05 0.2
0.1 0.25
0.1 0.5
0.5 1.0
0.25 0.5
0.5 0.9
1.25
0.25 0.0 +0.25
0.65 0.0 +0.65
2.0
1.5
0.15 1.0 1.2
0.15 1.0 1.2
0.5
25
200
PI6C3991-5
PI6C3991
Min. Typ. Max. Min. Typ. Max. Units
15 30 15 30
25 50 25 50 MHz
40 80 40 80
5.0 5.0
5.0 5.0
ns
See Table 1
See Table 1
0.1 0.25
0.1 0.25
0.25 0.5
0.3 0.75
0.6 0.7
0.6 1.0
0.5 1.0
1.0 1.5
0.5 0.7
0.7 1.2
0.5 1.0
1.2 1.7
1.25 1.65 ns
0.5 0.0 +0.5 0.7 0.0 +0.7
1.0 0.0 +1.0 1.2 0.0 +1.2
2.5 3
3.0 3.5
0.15 1.0 1.5 0.15 1.5 2.5
0.15 1.0 1.5 0.15 1.5 2.5
0.5 0.5 ms
25 25
ps
200 200
Notes:
7. Test measurement levels for the PI6C3991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2ns or less
and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified.
8. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters.
9. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has
been selected when all are loaded with 30pF and terminated with 50 Ohm to VCC/2.
10. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU.
11. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted.
12. CL = 0pF. For CL = 30pF, tSKEW0 = 0.35ns.
13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and Divided
(3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
14. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow,
etc.)
15. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4
specifications.
16. Specified with outputs loaded with 30pF for the PI6C3991 and PI6C3991-5 devices. Devices are terminated through 50 Ohm to VCC/
2. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
17. tORISE and tOFALL measured between 0.8V and 2.0V.
18. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within
normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within
specified limits.
5 PS8450B 04/09/01
5 Page 
PI6C3991
3.3V High-Speed, Low-Voltage Programmable
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122S1122k3344e55w667788C9900l11o2233c44k5566B7788u9900f11f22e3344r5566-77S8899u0011p22e1122r33C4455l66o77c8899k00®1122
Package Diagram - 32-Pin PLCC (J)
www.DataSheet4U.com
Ordering Information
Accuracy (ps) Ordering Code
250 PI6C3991-2J
500 PI6C3991-5J
750 PI6C3991J
500 PI6C3991-5IJ
750 PI6C3991-IJ
Package Name
J32
J32
J32
J32
J32
Package Type
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
32-Pin Plastic Leaded Chip Carrier
Operating Range
Commercial
Commercial
Commercial
Industrial
Pericom Semiconductor Corporation
2380 Bering Drive • San Jose, CA 95131 • 1-800-435-2336 • Fax (408) 435-1100 • http://www.pericom.com
1 1 PS8450B 04/09/01
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet PI6C3991-5IJ.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PI6C3991-5IJ | 3.3V High-Speed/ Low-Voltage Programmable Skew Clock Buffer SuperClock | ETC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |