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PDF PI6C2516 Data sheet ( Hoja de datos )
| Número de pieza | PI6C2516 | |
| Descripción | Phase-Locked Loop Clock Driver with 16 Clock Outputs | |
| Fabricantes | Pericom Semiconductor Corporation | |
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PI6C25161122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Phase-Locked Loop Clock Driver
with 16 Clock Outputs
Product Features
High Performance Phase-Locked Loop Clock Distribution for
Synchronous DRAM, server and networking applications.
Zero Input-to-Output delay: Distribute One Clock Input
to four banks of four outputs, with separate output enables
for each bank.
Allow Clock Input to have Spread Spectrum modulation for
EMI reduction. The clock outputs track the Clock Input
modulation.
Maximum clock frequency of 150 MHz.
Low jitter: Cycle-to-Cycle jitter ±100ps max
Operates at 3.3V VCC
Available Packaging:
48-pin TSSOP (Thin Shrink Small Outline) (A)
Description
The PI6C2516 family is a low-skew, low jitter, phase-locked loop
(PLL) clock driver, distributing high-frequency clock signals for
SDRAM, server and networking applications. By connecting the
feedback FB_OUT output to the feedback FB_IN input, the propa-
gation delay from the CLK input to any clock output will be nearly
zero. This zero-delay feature allows the CLK input clock to be
distributed, providing 4 banks of four outputs.
For test purposes, the PLL can be bypassed by strapping the AVCC
to ground.
The PI6C2516 family has the same pinout as the TI CDC2516, with
the added feature of allowing Spread Spectrum clock input.
Pin Description
VCC
1Y0
1Y1
GND
GND
1Y2
1Y3
VCC
1G
GND
AVCC
CLK
AGND
AGND
GND
2G
VCC
2Y0
2Y1
GND
GND
2Y2
2Y3
VCC
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 48-Pin 39
11 A 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
4Y0
4Y1
GND
GND
4Y2
4Y3
VCC
4G
GND
AVCC
FB_IN
AGND
FB_OUT
GND
3G
VCC
3Y0
3Y1
GND
GND
3Y2
3Y3
VCC
Block Diagram
1G
2G
3G
4G
CLK
FB_IN
AVCC
PLL
4 1Y [0:3]
4 2Y [0:3]
4 3Y [0:3]
4 4Y [0:3]
FB_OUT
1 PS8440C 07/24/01
1 page  
PI6C2516
Phase-Locked Loop Clock Driver
with 16 Clock Outputs1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Timing Requirements (Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature)
Symbol
Parameter
Min.
Max.
Units
FCLKOP
tCLKAPP
tSTABLILIZATION
Operator clock frequency (1)
Application clock frequency(2,4)
Stabilization time after power up(3)
25 150
MHz
6 133
1 ms
DCYI
Input clock duty cycle
40 60 %
Notes:
1. Operating Clock Frequency indicates a range over which the PLL must be able to lock, but in which it is not
required to meet the other timing parameters (used for low-speed system debug).
2. Application Clock Frequency indicates a range over which the PLL must meet all of the timing parameters.
3. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications
for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable.
4. Frequency and loading condition should not exceed 0.85 watt power dissipation (package limitation). Please refer to Graph 1.
350
300
250
200
150
100
50
0
0
Load = 22pF
Load = 10pF
50 100
Clock Frequency (MHz)
150
Graph 1. Dynamic Current vs. Clock Frequency (VCC = 3.6V, TA = 25°C)
Switching Characteristics
(Over Recommended Ranges of Supply Voltage and Operating Free-Air Temperature, CL = 22pF) (1,3)
Parameter
From
(Input)
To
(Output)
VCC = 3.3V ± 0.165V
VCC = 3.3V ± 0.3V
Min. Typ. Max. Min. Typ. Max.
tphase error
tsk(O)(2)
CLKIN↑ = 100MHz
Any Y or FBOUT
FBIN↑
150
+170
200
Jitter(pk-pk)
F(CLKIN > 66MHz)
100
100
Duty cycle
F(CLKIN ≤ 66MHz)
F(CLKIN > 66MHz)
Any Y or FBOUT
45 55
45 55
tr CLKIN = 50 to 150MHz
tf from 20% to 80%
1.3 2.1 0.7
1.7 2.5 1.2
2.1
2.5
Notes:
1. These parameters are not production tested.
2. The tsk(O) specification is only valid for equal loading of all outputs.
3. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
Units
ps
%
ns
5 PS8440C 07/24/01
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet PI6C2516.PDF ] | |
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