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PI6C2408-4L の電気的特性と機能

PI6C2408-4LのメーカーはPericom Semiconductor Corporationです、この部品の機能は「Zero-Delay Clock Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 PI6C2408-4L
部品説明 Zero-Delay Clock Buffer
メーカ Pericom Semiconductor Corporation
ロゴ Pericom Semiconductor Corporation ロゴ 




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PI6C2408-4L Datasheet, PI6C2408-4L PDF,ピン配置, 機能
PI6C24081122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Zero-Delay Clock Buffer
Features
Maximum rated frequency: 140 MHz
Low cycle-to-cycle jitter
Input to output delay, less than 150ps
External feedback pin allows outputs to be synchronized
to the clock input
5V tolerant input*
Operates at 3.3V VDD
Test mode allows bypass of the PLL for system testing
purposes (e.g., IBIS measurements)
Clock frequency multipliers ½x to 4x dependent on option
Packaging (Pb-free and Green available):
-16-pin, 150-mil SOIC (W)
-16-pin173-milTSSOP (L)
* FB_IN and CLKIN must reference the same voltage thresh-
olds for the PLL to deliver zero delay skewing
Block Diagram
FB_IN
CLKIN
÷2 PLL
Option (-3, -4)
SEL1
SEL2
Decode
Logic
MUX
÷2
Option (-2, -3)
PI6C2408 (-1, -1H, -2, -3, -4)
FB_IN
CLKIN
PLL
MUX
SEL2
SEL1
Decode
Logic
PI6C2408-6
÷2
MUX
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
OUTA1
OUTA2
OUTA3
OUTA4
OUTB1
OUTB2
OUTB3
OUTB4
Description
The PI6C2408 is a PLL-based, zero-delay buffer, with the ability
to distribute eight outputs of up to 140 MHz at 3.3 V. Two banks of
four outputs exist, and, depending on product option ordered, can
supply either reference frequency, prescaled half frequency, or
multiplied2xor4xinputclockfrequencies. ThePI6C2408familyhas
a power-sparing feature: when input SEL2 is 0, the component will
3-state one or both banks of outputs depending on the state of input
SEL1. A PLL bypass test mode also exists. This product line is
available in high-drive and industrial environment versions.
An external feedback pin is used to synchronize the outputs to the
input; the relationship between loading of this signal and the other
outputs determines the input-output delay.
The PI6C2408 is characterized for both commercial and industrial
operation.
Pin Configuration
CLKIN
OUTA1
OUTA2
VDD
GND
OUTB1
OUTB2
SEL2
1 16
2 15
3 14
4 16-Pin 13
5 W, L 12
6 11
7 10
89
FB_IN
OUTA4
OUTA3
VDD
GND
OUTB4
OUTB3
SEL1
1 PS8589E 09/15/04

1 Page





PI6C2408-4L pdf, ピン配列
PI6C2408
Zero Delay Clock Buffer1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
Pin Description
Pin
1
2, 3, 14, 15
4, 13
5, 12
6, 7, 10 ,11
8
9
16
Signal
CLKIN
OUTA[1-4]
VDD
GND
OUTB[1-4]
SEL2
SEL1
FB_IN
Description
Input clock reference frequency (weak pull-down)
Clock output, Bank A (weak pull-down)
3.3V supply
Ground
Clock output, Bank B (weak pull-down)
Select input, bit 2 (weak pull-up)
Select input, bit 1 (weak pull-up)
PLL feedback input
Zero Delay and Skew Control
CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins
800
600
400
200
0
-25 -20 -15 -10
-5
0
5 10 15 20 25
-200
-400
-600
PI6C2408-1H
-800
-900
PI6C2408-1,2,3,4,6
-1000
Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF)
The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when
all outputs, including feedback, are loaded equally.
Maximum Ratings
Supply Voltage to Ground Potential ............................................................................................................................. –0.5Vto+7.0V
DC Input Voltage (Except CLKIN) ........................................................................................................................ –0.5VtoVDD+0.5V
DC Input Voltage CLKIN ...................................................................................................................................................... –0.5 to 7V
Storage Temperature ................................................................................................................................................... –65ºC to +150ºC
Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260ºC
Junction Temperature .................................................................................................................................................................. 150ºC
Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V
3 PS8589E 09/15/04


3Pages


PI6C2408-4L 電子部品, 半導体
PI6C2408
Zero Delay Clock Buffer1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
DC Electrical Characteristics for Commercial Temperature Devices
Parameter
Description
Test Conditions
VIL
VIH
IIL
IIH
VOL
VOH
IDD (PD mode)
IDD
IDD
Input LOW Voltage
Input HIGH Voltage
Input LOW Current
Input HIGH Current
Output LOW Voltage
Output HIGH Voltage
Power Down Supply Current
Supply Current
Supply Current
VIN = 0V
VIN = VDD
IOL = 8mA (–1, –2, –3,–4, –6); IOL = 12mA (–1H)
IOH = –8mA (–1, –2, –3,–4, –6); IOH = –12mA (–1H)
SEL1 = 0 (-1,-2,-3,-4,-1H); SEL2 = 0 (-6)
Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND
Unloaded outputs 100 MHz Select Inputs @ VDD or GND
Min.
2.0
2.4
Max.
0.8
50
100
0.4
12
39
54
Units
V
µA
V
µA
mA
AC Electrial Characteristicsfor Commercial Temperature Device
Parameters
Name
Test Conditions
Min. Typ. Max. Units
FO
tDC
tR
tF
tSK(O)
t0
Output Frequency
30pF load
15pF load
Duty Cycle(1) (–1H)
Duty Cycle (–1, –2, –3, –4, –6)
Rise Time(1) @30pF
Measured at VDD/2, for high drive output
Measured at VDD/2, for normal drive output
Rise Time(1) @15pF
Rise Time(1) @30pF (–1H)
Fall Time(1) @30pF
Measured between 0.8V and 2.0V
Fall Time(1) @15pF
Fall Time(1) @30pF (–1H)
Output to Output Skew(1) within same
bank (–1,–1H,–2,–3,–4,–6)
All outputs equally loaded, VDD/2
OUTA to OUTB Skew(1) (–1,–1H,–4) All outputs equally loaded, VDD/2
OUTA to OUTB Skew(1) (–2,–3,–6) All outputs equally loaded, VDD/2
Input to Output Delay, CLKIN
Rising Edge to FB_IN Rising Edge(1)
Measured at VDD/2
10
100
140
MHz
45 50 55 %
40 50 60
2.2
1.5
1.5 ns
2.2
1.5
1.25
200
200
400 ps
0 ±150
tSK(D)
tSLEW
tJIT
tLOCK
Device to Device Skew(1)
Output Slew Rate(1)
Cycle-to-Cycle Jitter (1)(–1,–1H,–4)
Cycle-to-Cycle Jitter(1) (–2,–3,–6)
PLL Lock Time(1)
Measured at VDD/2 on FB_IN pins of devices
Measured between 0.8V and 2.0V on –1H
device using Test Circuit #2
Measured at 66.67 MHz, loaded 30pF outputs
Measured at 140 MHz, loaded 15pF outputs
Measured at 66.7 MHz, loaded 30pF outputs
Stable power supply, valid clocks
presented on CLKIN and FB_IN pins
1
0 500
V/ns
200
100 ps
400
1.0 ms
Notes:
1. See Switching Waveforms on page 7.
6 PS8589E 09/15/04

6 Page



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共有リンク

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