PDF PI6C2405A-1HL Data sheet ( Hoja de datos )

Número de pieza	PI6C2405A-1HL
Descripción	Zero-Delay Clock Buffer
Fabricantes	Pericom Semiconductor Corporation
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No Preview Available ! PI6C2405A Zero-Delay Clock Buffer Features • Maximum rated frequency: 133 MHz • Low cycle-to-cycle jitter • Input to output delay, less than 300ps • Internal feedback allows outputs to be synchronized to the clock input • 5V tolerant input* • Spread spectrum clock ready • Operates at 3.3V VDD • Packaging (Pb-free & Green available): -8-pin, 150-mil SOIC (W) -8-pin, 173-mil TSSOP (L) Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is used to synchronize the out- puts to the input; the relationship between loading of this signal and the outputs determines the input-output delay. PI6C2405A is able to track spread spectrum clocking for EMI reduction. PI6C2405A is characterized for both commercial and industrial operation. PI6C2405A-1H is a high-drive version of PI6C2405A-1 * CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing Block Diagram Pin Configuration CLKIN PLL PI6C2405A(–1, –1H) OUT0 OUT1 OUT2 OUT3 OUT4 CLKIN OUT2 OUT1 GND 1 2 3 4 8 OUT0 7 OUT4 6 VDD 5 OUT3 Pin Description Pin Signal 1 CLKIN 2, 3, 5, 7 OUT[1-4] 4 GND 6 VDD 8 OUT0 Description Input clock reference frequency (weak pull-down) Clock Outputs Ground 3.3V Supply Clockoutput, internal PLL feedback (weak pull-down) 1 PS8592D 09/22/04 1 page PI6C2405A Zero Delay Clock Buffer Switching Waveforms Duty Cycle Timing All Outputs Rise/Fall Time Output-Output Skew VDD/2 thigh VDD/2 tlow VDD/2 OUTPUT OUTPUT OUTPUT 2.0V 0.8V tR VDD/2 2.0V 0.8V tF VDD/2 tSK(O) 0V Device-Device Skew OUTPUT Device 1 VDD/2 OUTPUT Device 2 Input-Output Propagation Delay INPUT OUTPUT VDD/2 VDD/2 tSK(D) VDD/2 t0 tDC = thigh thigh+tlow 3.3V 0.1µF 0.1µF VDD OUTPUTS VDD GND GND CLK out CLOAD Test Circuit 1 Test Circuit for all parameters except tSLEW 0.1µF 0.1µF VDD OUTPUTS VDD GND GND 1k-ohm CLK out 1k-ohm 10pF Test Circuit 2 Test Circuit for tSLEW ,Output slew rate on –1H device 5 PS8592D 09/22/04 5 Page

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Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
PI6C2405A-1HL	Zero-Delay Clock Buffer	Pericom Semiconductor Corporation
PI6C2405A-1HLE	Zero-Delay Clock Buffer	Pericom Semiconductor Corporation
PI6C2405A-1HLI	Zero-Delay Clock Buffer	Pericom Semiconductor Corporation
PI6C2405A-1HLIE	Zero-Delay Clock Buffer	Pericom Semiconductor Corporation

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