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PDF PI6C103 Data sheet ( Hoja de datos )
| Número de pieza | PI6C103 | |
| Descripción | Precision Clock Synthesizer | |
| Fabricantes | Pericom Semiconductor Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de PI6C103 (archivo pdf) en la parte inferior de esta página. Total 12 Páginas | ||
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Precision Clock Synthesizer
for Mobile PCs
Features
Two copies of CPU clock
100 MHz or 66.6 MHz operation
Six copies of PCI clock, (synchronous with CPU clock)
Two copies of REF clock @ 14.31818 MHz
One copy of 48 MHz
One copy of selectable 48/24 MHz
Power management control input pins
Isolated core VDD, VSS pins for noise reduction
28-pin SSOP (H) and TSSOP (L) packages
SSC Options:
Device
PI6C103
PI6C103-05
PI6C103-06
66 MHz
0.67%
1.35%
1.79%
100 MHz
0.65%
1.35%
1.79%
Description
The PI6C103 is a high-speed, low-noise clock generator designed
to work with the PI6C18X clock buffer to meet all clock needs
for Mobile Intel Architecture platforms. System clock frequencies
of 66.6 MHz and 100 MHz are supported.
Split supplies of 3.3V and 2.5V are used. The 3.3V power supply
powers everything except the CPU clock. The 2.5V power supply is
used to power the CPUCLK outputs. 2.5V signaling follows JEDEC
standard 8-X. Power sequencing of the 3.3V and 2.5V supplies is
not required.
An asynchronous PWR_DWN# signal may be used to orderly
power down (or up) the system. CPU and PCI clocks may also be
stopped by the CPU_STOP# and PCI_STOP# signals.
The PI6C103 contains the Spread Spectrum function for only those
clocks that synchronize to the CPU clocks (CPU and PCI clocks).
Block Diagram
Pin Configuration
XTAL_IN
XTAL_OUT
REF
OSC
SPREAD#
SEL100/66#
PLL1
DIV CPU_STOP#
PCI_STOP#
PWR_DWN#
TS#
PLL2
SEL48#
MUX
÷2
2 REF
[0:1]
2 CPUCLK
[0:1]
5 PCICLK
[1:5]
PCICLK_F
48 MHz
48/24 MHz
VSS
XTAL_IN
XTAL_OUT
PCICLK_F
PCICLK1
PCICLK2
VSS
VDD
PCICLK3
PCICLK4
PCICLK5
VDD
48 MHz
48-24MHz/TS#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-Pin
H, L
28 VDD
27 REF1/SEL48#
26 REF0/Spread#
25 VDD2
24 CPUCLK0
23 CPUCLK1
22 VSS2
21 VSS
20 PCI_STOP#
19 VDD
18 CPU_STOP#
17 PWR_DWN#
16 SEL100/66#
15 VSS
222
PS8315-2 04/08/99
1 page  
PI6C103
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PCI_STOP# is an input signal used to turn off PCI clocks for low with a guaranteed full high pulse width. There is ONLY one rising
power operation. PCI clocks are stopped in the low state and started edge of external PCICLK after the clock control logic.
CPUCLK
(Internal)
PCICLK
(Internal)
PCICLK_F
(Free-running)
CPU_STOP#
PCI_STOP#
PWR_DWN#
PCICLK
(External)
Notes:
PCI_STOP# Timing Diagram
1. All timing is referenced to the CPUCLK.
2. PCI_STOP# signal is an input signal which must be made synchronous to PCI_F output.
3 Internal means inside the chip.
4. All other clocks continiue to run undisturbed.
5. PWR_DWN# CPU_STOP# are shown in a high state.
6. Diagrams shown with respect to 66 MHz. Similar operation as CPU = 100 MHz.
The PWR_DWN# is used to place the device in a very low power The power-on latency is less than 3ms. PCI_STOP# and
state. PWR_DWN# is an asynchronous active low input. Internal CPU_STOP# are dont cares during the power-down operations.
clocks are stopped after the device is put in power-down mode. The REF clock is stopped in the LOW state as soon as possible.
CPUCLK
(Internal)
PCICLK
(Internal)
PWR_DWN#
CPUCLK
(External)
PCICLK
(External)
VCO
Crystal
Notes:
PWR_DWN# Timing Diagram
1. All timing is referenced to the CPUCLK.
2. The Internal label means inside the chip and is a reference only.
3. PWR_DWN# is an asynchronous input and metastable conditions could exist. The signal is synchronized inside the part.
4. The Shaded sections on the VCO and the Crystal signals indicate an active clock.
5. Diagrams shown wth respect to 66 MHz. Similar operations as CPU = 100 MHz.
226
PS8315-2 04/08/99
5 Page 
PI6C103
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PCB Layout Suggestion
FB1
VCC
C1
22µF
C2 VSS
VDD
C3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
C6
28 VDD
27
26
C5
25 VDD
24
23
22 VSS
21 VSS
20
C4
19 VDD
18
17
16
15 VSS
FB2 VCC
C7
22µF
Via to VDD Plane
Via to GND Plane
Void in Power Plane
Note:
This is only a suggested layout. There may be alternate solutions
depending on actual PCB design and layout.
As a general rule, C2-C6 should be placed as close as possible to
their respective VDD.
Recommended capacitor values:
C2-C6 ............... 0.1µF, ceramic
C1, C7 ............ 22µF
232
PS8315-2 04/08/99
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet PI6C103.PDF ] | |
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