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PDF MH8S72DBFD-7 Data sheet ( Hoja de datos )
| Número de pieza | MH8S72DBFD-7 | |
| Descripción | 603 /979 /776-BIT ( 8 /388 /608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
DESCRIPTION
The MH8S72DBFD is 8388608 - word x 72-bit Sy nchronous
DRAM module. This consist of nine industry standard
8M x 8 Sy nchronous DRAMs in TSOP.
The TSOP on a card edge dual in-line package prov ides any
application where high densities and large of quantities memory
are required.
This is a socket-ty pe memory m odule ,suitable f or easy
interchange or addition of m odule.
FEATURES
Type name
MH8S72DBFD-7
MH8S72DBFD-8
Max.
Frequency
100MHz
100MHz
CLK
Access Time
[component level]
6ns (CL = 2, 3)
6ns (CL = 3)
Utilizes industry standard 8M X 8 Synchronous DRAMs in
TSOP package , industry standard Resistered buffer in TSSOP
package and industry standard PLL in TSSOP package
Single 3.3V +/- 0.3V supply
LVTTL Interface
Burst length 1/2/4/8/Full Page(programmable)
Burst W rite / Single W rite(programmable)
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycles every 64ms
Discrete IC and module design conform to
PC/100 specification.
(module Spec. Rev. 1.2 and SPD 1.2A)
APPLICATION
Main memoryor graphic memoryin computer systems
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999 1
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
BASIC FUNCTIONS
The MH8S72DBFD provides basic functions,bank(row)activate,burst read / write,
bank(row)precharge,and auto / self refresh.
Each command is defined by control signals of /RAS,/CAS and /WE at CK rising edge. In
addition to 3 signals,/S,CKE and A10 are used as chip select,refresh option,and precharge
option,respectively.
To know the detailed definition of commands please see the command truth table.
CK
/S
/RAS
/CAS
/WE
CKE
A10
Chip Select : L=select, H=deselect
Command
Command def ine basic commands
Command
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate(ACT) [/RAS =L, /CAS = /WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read(READ) [/RAS =H,/CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA.First output
data appears after /CAS latency. When A10 =H at this command,the bank is
deactivated after the burst read(auto-precharge,READA).
Write(WRITE) [/RAS =H, /CAS = /WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data
length to be written is set by burst length. When A10 =H at this command, the bank
is deactivated after the burst write(auto-precharge,WRITEA).
Precharge(PRE) [/RAS =L, /CAS =H,/WE =L]
PRE command deactivates the active bank indicated by BA. This command also
term inates burst read / write operation. When A10 =H at this command, both banks
are deactivated(precharge all, PREA).
Auto-Refresh(REFA) [/RAS =/CAS =L, /WE =CKE =H]
PEFA command starts auto-refresh cycle. Refresh address including bank address
are generated internally. After this command, the banks are precharged automatically.
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999 5
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DBFD-7,-8
603,979,776-BIT ( 8,388,608-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
FUNCTION TRUTH TABLE FOR CKE
CKE CKE
Current State n-1 n
SELF -
HX
REFRESH*1 L H
LH
LH
LH
LH
LL
POWER
DOWN
HX
LH
LL
ALL BANKS H H
IDLE*2
HL
HL
HL
HL
HL
HL
ANY STATE
L
H
X
H
other than
HL
listed above
L
L
H
L
/S /RAS /CAS /WE Add
Action
X X X X X INVALID
H X X X X Exit Self-Refresh(Idle after tRC)
L H H H X Exit Self-Refresh(Idle after tRC)
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X NOP(Maintain Self-Refresh)
X X X X X INVALID
X X X X X Exit Power Down to Idle
X X X X X NOP(Maintain Self-Refresh)
X X X X X Refer to Function Truth Table
L L L H X Enter Self-Refresh
H X X X X Enter Power Down
L H H H X Enter Power Down
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
X X X X X Refer to Current State = Power Down
X X X X X Refer to Function Truth Table
X X X X X Begin CK0 Suspend at Next Cycle*3
X X X X X Exit CK0 Suspend at Next Cycle*3
X X X X X Maintain CK0 Suspend
ABBREVIATIONS:
H = High Level, L = Low Level, X = Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK and other inputs asynchronously.
A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only form the All banks idle State.
3. Must be legal command.
MIT-DS-0351-0.0
MITSUBISHI
ELECTRIC
30/Sep. /1999 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH8S72DBFD-7.PDF ] | |
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