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MH8S72DALD-7 の電気的特性と機能

MH8S72DALD-7のメーカーはMitsubishiです、この部品の機能は「603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 MH8S72DALD-7
部品説明 603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
メーカ Mitsubishi
ロゴ Mitsubishi ロゴ 




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MH8S72DALD-7 Datasheet, MH8S72DALD-7 PDF,ピン配置, 機能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
DESCRIPTION
The MH8S72DALD is 8388608 - word by 72-bit
Synchronous DRAM module. This consists of nine
industry standard 8Mx8 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Frequency
CLK Access Time
(Component SDRAM)
-6 133MHz 5.4ns(CL=3)
-7 100MHz 6.0ns(CL=2)
-8 100MHz 6.0ns(CL=3)
Utilizes industry standard 8M x 8 Sy nchronous DRAMs
TSOP and industry standard EEPROM in TSSOP
168-pin (84-pin dual in-line package)
single 3.3V±0.3V power supply
Max. Clock frequency -6:133MHz,-7,8:100MHz
Fully synchronous operation referenced to clock
rising edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
LVTTL Interface
Discrete IC and module design conform to
PC100/PC133 specification.
85pin 1pin
94pin
95pin
10pin
11pin
124pin 40pin
125pin 41pin
168pin 84pin
APPLICATION
PC main memory
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
17.Sep.1999

1 Page





MH8S72DALD-7 pdf, ピン配列
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
Block Diagram
/S0
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM /CS
I/O 0
I/O 1
I/O 2
D0
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D1
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQM /CS
I/O 0
I/O 1
I/O 2
D4
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D5
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
/S2
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQM /CS
I/O 0
I/O 1
I/O 2
D8
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D3
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CK0
CK2
CK1
5SDRAMs
4SDRAMs+3.3pF cap.
CK3
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQM /CS
I/O 0
I/O 1
I/O 2
D6
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQM /CS
I/O 0
I/O 1
I/O 2
D7
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
MIT-DS-0341-0.0
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
D0 - D8
CKE0
D0 - D8
MITSUBISHI
ELECTRIC
( 3 / 55 )
SCL
WP
47K
SERIAL PD
A0 A1 A2
SDA
SA0 SA1 SA2
17.Sep.1999


3Pages


MH8S72DALD-7 電子部品, 半導体
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S72DALD -6,-7,-8
603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM
PIN FUNCTION
CK
(CK0 ~ CK3)
CKE0
/S
(/S0,2)
/RAS,/CAS,/WE
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
BA0,1
DQ0-63
CB0-7
DQMB0-7
Vdd,Vs s
Input
Input
A0-11 specify the Row/Column Address in conjunction with
BA.The Row Address is specified by A0-11.The Column
Address is specified by A0-8.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, all banks are precharged.
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output Data In and Data out are referenced to the rising edge of
CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL Input Serial clock for serial PD
SDA
SA0-3
Output Serial data for serial PD
Input Address input for serial PD
MIT-DS-0341-0.0
MITSUBISHI
ELECTRIC
( 6 / 55 )
17.Sep.1999

6 Page



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共有リンク

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部品番号部品説明メーカ
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603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM

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MH8S72DALD-7

603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM

Mitsubishi
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MH8S72DALD-8

603979776-BIT (8388608 - WORD BY 72-BIT)Synchronous DRAM

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