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MH8S64DBKG-7L の電気的特性と機能

MH8S64DBKG-7LのメーカーはMitsubishiです、この部品の機能は「536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 MH8S64DBKG-7L
部品説明 536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
メーカ Mitsubishi
ロゴ Mitsubishi ロゴ 




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MH8S64DBKG-7L Datasheet, MH8S64DBKG-7L PDF,ピン配置, 機能
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
DESCRIPTION
The MH8S64DBKG is 8388608 - word by 64-bit
Synchronous DRAM module. This consists of eight
industry standard 4Mx16 Synchronous DRAMs in
TSOP and one industory standard EEPROM in
TSSOP.
The mounting of TSOP on a card edge Dual
Inline package provides any application where
high densities and large quantities of memory are
required.
This is a socket type - memory modules, suitable
for easy interchange or addition of modules.
FEATURES
Utilizes industry s t andard 4M x 16 Sy nchronous DRAMs
TSOP and industry s t andard EEPROM in TSSOP
144-pin (72-pin dual in-line package)
single 3.3V±0.3V power supply
Clock frequency 100MHz(max.)
Fully synchronous operation referenced to clock rising
edge
4 bank operation controlled by BA0,1(Bank Address)
/CAS latency- 2/3(programmable)
Burst length- 1/2/4/8/Full Page(programmable)
-7,-7L
-8,-8L
Frequency
CLK Access Time
(Component SDRAM)
100MHz
6.0ns(CL=2)
100MHz
6.0ns(CL=3)
Burst type- sequential / interleave(programmable)
Column access - random
Auto precharge / All bank precharge controlled by A10
Auto refresh and Self refresh
4096 refresh cycle /64ms
PC100 compliant
LVTTL Interface
APPLICATION
main memory or graphic memory in computer systems
PCB Outline
(Front)
(Back)
1
2
MIT-DS-0340-0.0
MITSUBISHI
ELECTRIC
( 1 / 55 )
143
144
17.Sep.1999

1 Page





MH8S64DBKG-7L pdf, ピン配列
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
Block Diagram
/S0
/S1
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D0
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D4
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB4
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB5
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D2
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D6
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
10
CLK1
CLK0
CKE0
CKE1
/RAS
/CAS
/WE
BA0,BA1,A<11:0>
Vcc
Vss
MIT-DS-0340-0.0
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D1
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D5
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
DQMB6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
4loads
4loads
D0 - D3
D4 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
D0 - D7
SCL
MITSUBISHI
ELECTRIC
( 3 / 55 )
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D3
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SERIAL PD
A0 A1 A2
DQML /CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
D7
DQMU
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
SDA
17.Sep.1999


3Pages


MH8S64DBKG-7L 電子部品, 半導体
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8S64DBKG -7,-7L,-8,-8L
536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM
PIN FUNCTION
CLK
(CLK0 ~ CLK1)
CKE0, CKE1
/S0, /S1
/RAS,/CAS,/WE
Input
Input
Input
Input
Master Clock:All other inputs are referenced to the rising
edge of CK
Clock Enable:CKE controls internal clock.When CKE is
low,internal clock for the following cycle is ceased. CKE is
also used to select auto / self refresh. After self refresh
mode is started, CKE E becomes asynchronous input.Self
refresh is maintained as long as CKE is low.
Chip Select: When /S is high,any command means
No Operation.
Combination of /RAS,/CAS,/WE defines basic commands.
A0-11
BA0,1
DQ0-63
DQMB0-7
Vdd,Vs s
Input
Input
A0-11 specify the Row/Column Address in conjunction with
BA0,1.The Row Address is specified by A0-11.The Column
Address is specified by A0-7.A10 is also used to indicate
precharge option.When A10 is high at a read / write
command, an auto precharge is performed. When A10 is
high at a precharge command, both banks are precharged.
Bank Address:BA0,1 is not simply BA.BA specifies the
bank to which a command is applied.BA0,1 must be set
with ACT,PRE,READ,WRITE commands
Input/Output Data In and Data out are referenced to the rising edge
of CK
Input
Din Mask/Output Disable:When DQMB is high in burst
write.Din for the current cycle is masked.When DQMB is
high in burst read,Dout is disabled at the next but one cycle.
Power Supply Power Supply for the memory mounted module.
SCL
Input Serial clock for serial PD
SDA
Output Serial data for serial PD
MIT-DS-0340-0.0
MITSUBISHI
ELECTRIC
( 6 / 55 )
17.Sep.1999

6 Page



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部品番号部品説明メーカ
MH8S64DBKG-7

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Mitsubishi
Mitsubishi
MH8S64DBKG-7

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Mitsubishi
Mitsubishi
MH8S64DBKG-7L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Mitsubishi
Mitsubishi
MH8S64DBKG-7L

536870912-BIT (8388608 - WORD BY 64-BIT)SynchronousDRAM

Mitsubishi
Mitsubishi


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