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PDF MH8D64AKQC-75 Data sheet ( Hoja de datos )
| Número de pieza | MH8D64AKQC-75 | |
| Descripción | 536 /870 /912-BIT (8 /388 /608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module | |
| Fabricantes | Mitsubishi | |
| Logotipo |  |
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
DESCRIPTION
The MH8D64AKQC is 8388608 - word x 64-bit Double
Data Rate(DDR) Sy nchronous DRAM mounted module.
This consists of 4 industry standard 8M x 16 DDR
Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which
achiev es v ery high speed data rate up to 133MHz.
This socket-ty pe memory m odule is suitable f or main
memory in computer systems and easy to interchange or
add modules.
FEATURES
Type name
MH8D64AKQC-75
MH8D64AKQC-10
Max.
Frequency
133MHz
100MHz
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
- Utilizes industry standard 8M X 16 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
- 200pin SO-DIMM
- Vdd=Vddq=2.5v ±0.2V
- Double data rate architecture; two data transf ers per
clock cy c le
- Bidirectional, data strobe (DQS) is transmitted/receiv ed
with data
- Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positiv e CLK edge
- Data and data mask ref erenced to both edges of DQS
- 4bank operation concontrolled by BA0,BA1(Bank Address
,discrete)
- /CAS latency - 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Ty pe - sequential/interleav e(programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 ref resh cy c les /64ms
- Auto ref resh and Self ref resh
- Row address A0-11 / Column address A0-8
- SSTL_2 Interf ace
- Module 1bank Conf igration
APPLICATION
Main memoryunit for Note PC, Mobile etc.
PCB Outline
(Front)
(Back)
1
2
199
200
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
1
1 page  
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH8D64AKQC provides basic functions, bank (row) activate, burst read / write, bank (row)
precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS
and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip
select, refresh option, and precharge option, respectively. To know the detailed definition of
commands, please see the command truth table.
/CK0
CK0
/S0
/RAS
/CAS
/WE
CKE0
A10
Chip Select : L=select, H=deselect
Command
Command
Command
def ine basic commands
Ref resh Option @ref resh command
Precharge Option @precharge or read/write command
Activate (ACT) [/RAS =L, /CAS =/WE =H]
ACT command activates a row in an idle bank indicated by BA.
Read (READ) [/RAS =H, /CAS =L, /WE =H]
READ command starts burst read from the active bank indicated by BA. First output data
appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the
burst read (auto-precharge,READA)
Write (WRITE) [/RAS =H, /CAS =/WE =L]
WRITE command starts burst write to the active bank indicated by BA. Total data length to be
written is set by burst length. When A10 =H at this command, the bank is deactivated after
the burst write (auto-precharge, WRITEA).
Precharge (PRE) [/RAS =L, /CAS =H, /WE =L]
PRE command deactivates the active bank indicated by BA. This command also terminates
burst read /write operation. When A10 =H at this command, all banks are deactivated
(precharge all, PREA).
Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H]
REFA command starts auto-refresh cycle. Refresh address including bank address are
generated internally. After this command, the banks are precharged automatically.
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
5
5 Page 
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
CKE0 CKE0
Current State n-1 n /S0 /RAS /CAS /WE Add
Action
Notes
SELF-
REFRESH
H X X X X X X INVALID
L H H X X X X Exit Self-Refresh (Idle after tRC)
L H L H H H X Exit Self-Refresh (Idle after tRC)
L H L H H L X ILLEGAL
L H L H L X X ILLEGAL
L H L L X X X ILLEGAL
L L X X X X X NOP (Maintain Self-Refresh)
1
1
1
1
1
1
1
POWER
DOWN
H X X X X X X INVALID
L H X X X X X Exit Power Down to Idle
L L X X X X X NOP (Maintain Self-Refresh)
ALL BANKS H H X X X X X Refer to Function Truth Table
IDLE
H L L L L H X Enter Self-Refresh
H L H X X X X Enter Power Down
H L L H H H X Enter Power Down
2
2
2
2
HL
HL
HL
L H H L X ILLEGAL
L H L X X ILLEGAL
L L X X X ILLEGAL
2
2
2
L X X X X X X Refer to Current State =Power Down 2
ANY STATE H H X X X X X Refer to Function Truth Table
other than H L X X X X X Begin CLK Suspend at Next Cycle 3
listed above L H X X X X X Exit CLK Suspend at Next Cycle
3
L L X X X X X Maintain CLK Suspend
ABBREVIATIONS:
H=High Level, L=Low Level, X=Don't Care
NOTES:
1. CKE Low to High transition will re-enable CK0 and other inputs asynchronously
. A minimum setup time must be satisfied before any command other than EXIT.
2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State.
3. Must be legal command.
MIT-DS-0419-0.1
MITSUBISHI
ELECTRIC
17.May.2001
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MH8D64AKQC-75.PDF ] | |
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