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PDF MH89760B Data sheet ( Hoja de datos )
| Número de pieza | MH89760B | |
| Descripción | ST-BUS FAMILY T1/ESF Framer & Interface Preliminary Information | |
| Fabricantes | Mitel Networks | |
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ST-BUS™ FAMILY MH89760B
® T1/ESF Framer & Interface
Preliminary Information
Features
• Complete interface to a bidirectional T1 link
• D3/D4 or ESF framing and SLC-96 compatible
• Two frame elastic buffer with 32µs jitter buffer
• Insertion and detection of A, B, C, D bits
Signalling freeze, optional debounce
• Selectable B8ZS, jammed bit (ZCS) or no zero
code suppression
• Yellow and blue alarm signal capabilities
• Bipolar violation count, FT error count, CRC
error count
• Frame and superframe sync. signals, Tx and Rx
• Per channel, overall, and remote loop around
• 8 kHz synchronization output
• Digital phase detector between T1 line and ST-
BUS
• ST-BUS compatible
• Pin compatible with the MH89760
• Inductorless clock recovery
• Loss of Signal (LOS) indication
• Available in standard, narrow and surface
mount formats
Applications
• DS1/ESF digital trunk interfaces
• Computer to PBX interfaces (DMI and CPI)
• High speed computer to computer data links
ISSUE 5
May 1995
MH89760B
MH89760BN
MH89760BS
Ordering Information
40 Pin DIL Hybrid 1.3" row pitch
40 Pin DIL Hybrid 0.8" row pitch
40 Pin Surface Mount Hybrid
0°C to 70°C
Description
The MH89760B is a complete T1 interface solution,
meeting the Extended Super Frame (ESF), D3/D4
and SLC-96 formats. The MH89760B interfaces to
the DS11.544 Mbit/sec digital trunk.
The MH89760B is a pin-compatible enhancement of
the MH89760, permitting the removal of the tuneable
inductor and inclusion of the external NAND gate
used for generating RxD.
TxSF
C2i
F0i
RxSF
DSTo
DSTi
CSTi0
CSTi1
CSTo
ST-BUS
Timing
Circuitry
Data
Interface
Serial
Control
Interface
VDD
XCtl
XSt
Control
Logic
1544-2048
Two Frame
Elastic
Buffer
2048 - 1544
Converter
DS1
LINK
INTERFACE
Transmitter
Receiver
ABCD
Signalling RAM
Phase
Detector
Clock
Extractor
DS1
Counter
Figure 1 - Functional Block Diagram
C1.5i
RxFDLClk
RxFDL
TxFDLClk
TxFDL
OUTA
OUTB
RxA
RxT
LOS
RxR
RxB
E1.5o
E8Ko
VSS
4-55
1 page  
Preliminary Information
MH89760B
Functional Description
The MH89760B is a thick film hybrid solution for a T1
interface. All of the formatting and signalling
insertion and detection is done by the device.
Various programmable options in the device include:
ESF, D3/D4 or SLC-96 mode, common channel or
robbed bit signalling, zero code suppression, alarms,
and local and remote loopback. The MH89760B also
has built in bipolar line drivers and receivers and a
clock extraction circuit.
All data and control information is communicated to
the MH89760B via 2048 kbit/s serial streams
conforming to Mitel’s ST-BUS format.
The ST-BUS is a TDM serial bus that operates at
2048 kbits/s. The serial streams are divided into 125
µsec frames that are made up of 32 8-bit channels. A
serial stream that is made up of these 32 8 bit
channels is known as an ST-BUS stream, and one of
these 64 kbit/s channels is known as an ST-BUS
channel.
The system side of the MH89760B is made up of ST-
BUS inputs and outputs, i.e., control inputs and
outputs (CSTi/o) and data inputs and outputs
(DSTi/o). These signals are functionally represented
in Figure 32. The DS1 line side of the device is made
up of split phase inputs (RxT, RxR) and outputs
(OUTA, OUTB) which can be connected to line
coupling transformers. Functional transmit and
receive timing is shown in Figures 33 and 34.
Data for transmission on the DS1 line is clocked
serially into the device at the DSTi pin. The DSTi pin
accepts a 32 channel time division multiplexed ST-
BUS stream. Data is clocked in with the falling edge
of the C2i clock. ST-BUS frame boundaries are
defined by the frame pulse applied at the F0i pin.
Only 24 of the available 32 channels on the ST-BUS
serial stream are actually transmitted on the DS1
side. The unused 8 channels are ignored by the
device.
Data received from the DS1 line is clocked out of the
device in a similar manner at the DSTo pin. Data is
clocked out on the rising edge of the C2i clock. Only
24 of the 32 channels output by the device contain
the information from the DS1 line. The DSTo pin is,
however, actively driven during the unused channel
timeslots. Figure 3 shows the correspondence
between the DS1 channels and the ST-BUS
channels.
All control and monitoring of the device is
accomplished through two ST-BUS serial control
inputs and one serial control output. Control ST-BUS
input number 0 (CSTi0) accepts an ST-BUS serial
stream which contains the 24 per channel control
words and two master control words. The per channel
control words relate directly to the 24 information
channels output on the DS1 side. The master control
words affect operation of the whole device. Control
ST-BUS input number 1 (CSTi1) accepts an ST-BUS
stream containing the A, B, C and D signalling bits.
The relationship between the CSTi channels and the
controlled DS0 channels is shown in Figure 3. Status
and signalling information is received from the device
via the control ST-BUS output (CSTo). This serial
output stream contains two master status words, 24
per channel status words and one Phase Status
Word. Figure 3 shows the correspondence between
the received DS1 channels and the status words.
Detailed information on the operation of the control
interface is presented below.
Programmable Features
The main features in the device are programmed
through two master control words which occupy
channels 15 and 31 in Control ST-BUS input stream
number 0 (CSTi0). These two eight bit words are
used to:
• Select the different operating modes of the
device ESF, D3/D4 or SLC-96.
• Activate the features that are needed in a
certain application; common channel signalling,
zero code suppression, signalling debounce,
etc.
• Turn on in service alarms, diagnostic loop
arounds, and the external control function.
Tables 1 and 2 contain a complete explanation of the
function of the different bits in Master Control Words
1 and 2.
Major Operating Modes
The major operating modes of the device are
enabled by bits 2 and 4 of Master Control Word 2.
The Extended Superframe (ESF) mode is enabled
when bit 4 is set high. Bit 2 has no effect in this
mode. The ESF mode enables the transmission of
the S bit pattern shown in Table 3. This includes the
frame/superframe pattern, the CRC-6, and the
Facility Data Link (FDL). The device generates the
frame/multiframe pattern and calculates the CRC for
each superframe. The data clocked into the device
on the TxFDL pin is incorporated into the FDL. ESF
mode will also insert A, B, C and D signalling bits into
the 24 frame multiframe. The DS1 frame begins after
approximately 25 periods of the C1.5i clock from the
F0i frame pulse.
4-59
5 Page 
Preliminary Information
MH89760B
Bit Name
Description
.
7-4
Unused
Unused Bits. Will be output as 0’s.
3 A These are the 4 signalling bits as extracted from the received DS1 bit stream.
2 B The bits are debounced for 6 to 9 ms if the debounce feature is enabled via bit 7 in Master
1 C Control Word 1.
0D
Table 11. Per Channel Status Word Output on CSTo
Alarm Detection
The device detects the yellow alarm for both D3/D4
frame format and ESF format. The D3/D4 yellow
alarm will be activated if a ‘0‘ is received in bit
position 2 of every DS0 channel for 600 msec. It will
be released in 200 msec after the contents of the bit
change. The alarm is detectable in the presence of
errors on the line. The ESF yellow alarm will
become active when the device has detected a string
of eight 0’s followed by eight 1’s in the facility data
link. It is not detectable in the presence of errors on
the line. This means that the ESF yellow alarm will
drop out for relatively short periods of time, so the
system will have to integrate the ESF yellow alarm.
The blue alarm signal, in Master Status Word 2, will
also drop out if there are errors on the line.
Mimic Detection
The mimic bit in Master Status Word 1 will be set if,
during synchronization, a frame alignment pattern
(FT or FPS bit pattern) was observed in more than
one position, i.e., if more than one candidate for the
frame synchronization position was observed. It will
be reset when the device resynchronizes. The mimic
bit, the terminal framing error bit and the CRC error
counter can be used separately or together to decide
if the receiver should be forced to reframe.
Bipolar Violation Counter
The Bipolar Violation bit in Master Status Word 1 will
toggle after 256 violations have been detected in the
received signal. It has a maximum refresh time of 96
ms. This means that the bit can not change state
faster than once every 96 ms. For example, if there
are 256 violations in 80 ms the BPV bit will not
change state until 96 ms. Any more errors in that
extra 16 ms are not counted. If there are 256 errors
in 200 ms then the BPV bit will change state after
200 ms. In practical terms this puts an upper limit
on the error rate that can be calculated from the BPV
information, but this rate (1.7 X 10-3) is well above
any normal operating condition.
Bits 4 and 3 also provide bipolar violations infor-
mation. Bit 4 will change state after 128 violations.
Bit 3 changes state after 64 bipolar violations. These
bits are refreshed independently and are not subject
to the 96 ms refresh rate described above.
DS1/ST-BUS Phase Difference
An indication of the phase difference between the
ST-BUS and the DS1 frame can be ascertained from
the information provided by the eight bit Phase
Status Word and the Frame Count bit. Channel three
on CSTo contains the Phase Status Word. Bits 7-3 in
this word indicate the number of ST-BUS channels
between the ST-BUS frame pulse and the rising
edge of the E8Ko signal. The remaining three bits
provide one bit resolution within the channel count
indicated by bits 7-3. The frame count bit in Master
Status Word 2 is the ninth and most significant bit of
the phase status word. It will toggle when the phase
status word increments above channel 31, bit 7 or
decrements below channel 0, bit 0. The E8Ko signal
has a specific relationship with received DS1 frame.
The rising edge of E8Ko occurs during bit 2, channel
17 of the received DS1 frame. The Phase Status
Word in conjunction with the frame count bit, can be
used to monitor the phase relationship between the
received DS1 frame and the local ST-BUS frame.
The local 2.048 MHz ST-BUS clock must be phase-
locked to the 1.544 MHz clock extracted from the
received data. When the two clocks are not phase-
locked, the input data rate on the DS1 side will differ
from the output data rate on the ST-BUS side. If the
average input data rate is higher than the average
output data rate, the channel count and bit count in
the phase status word will be seen to decrease over
time, indicating that the E8Ko rising edge, and
therefore the DS1 frame boundary is moving with
respect to the ST-BUS frame pulse. Conversely, a
lower average input data rate will result in an
increase in the phase reading.
In an application where it is necessary to minimize
jitter transfer from the received clock to the local
system clock, a phase lock loop with a relatively
large time constant can be implemented using
information provided by the phase status word. In
such a system, the local 2.048 MHz clock is derived
from a precision VCO. Frequency corrections are
made on the basis of the average trend observed in
4-65
11 Page | ||
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| PDF Descargar | [ Datasheet MH89760B.PDF ] | |
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