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PDF MAX101A Data sheet ( Hoja de datos )
| Número de pieza | MAX101A | |
| Descripción | 500Msps / 8-Bit ADC with Track/Hold | |
| Fabricantes | Maxim Integrated | |
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19-1109; Rev 0; 7/96
EVALUAATVIOANILKAIBTLMEANUAL
500Msps, 8-Bit ADC with Track/Hold
_______________General Description
The MAX101A ECL-compatible, 500Msps, 8-bit analog-
to-digital converter (ADC) allows accurate digitizing of
analog signals from DC to 250MHz (Nyquist frequen-
cy). Dual monolithic converters, driven by the track/hold
(T/H), operate on opposite clock edges (time inter-
leaved). Designed with Maxim’s proprietary advanced
bipolar processes, the MAX101A contains a high-per-
formance T/H amplifier and two quantizers in an 84-pin
ceramic flat pack.
The innovative design of the internal T/H ensures an
exceptionally wide 1.2GHz input bandwidth and aper-
ture delay uncertainty of less than 2ps, resulting in a
high 7.0 effective bits at the Nyquist frequency. Special
comparator output design and decoding circuitry
reduce out-of-sequence code errors. The probability of
erroneous codes due to metastable states is reduced to
less than 1 error per 1015 clock cycles. And, unlike other
ADCs that can have errors resulting in false full-scale or
zero-scale outputs, the MAX101A keeps the error mag-
nitude to less than 1LSB.
The analog input is designed for either differential or
single-ended use with a ±250mV range. Sense pins for
the reference input allow full-scale calibration of the
input range or facilitate ratiometric use.
Phase adjustment is available to adjust the relative
sampling of the converter halves for optimizing convert-
er performance. Input clock phasing is also available
for interleaving several MAX101As for higher effective
sampling rates.
____________________________Features
o 500Msps Conversion Rate
o 7.0 Effective Bits Typical at 250MHz
o 1.2GHz Analog Input Bandwidth
o Less than ±1/2LSB INL
o 50Ω Differential or Single-Ended Inputs
o ±250mV Input Signal Range
o Ratiometric Reference Inputs
o Dual Latched Output Data Paths
o Low Error Rate, Less than 10-15 Metastable States
o 84-Pin Ceramic Flat Pack
________________________Applications
High-Speed Digital Instrumentation
High-Speed Signal Processing
Medical Systems
Radar/Signal Processing
High-Energy Physics
Communications
______________Ordering Information
PART
TEMP. RANGE
PIN-PACKAGE
MAX101ACFR*
0°C to +70°C
84 Ceramic Flat Pack
(with heatsink)
*Contact factory for 84-pin ceramic flat pack without heatsink.
_________________________________________________________Functional Diagram
MAX101A
AIN+
AIN-
TRACK
AND
HOLD
CLK
CLK
VART VARTS
STROBE
TRK1 TRK1 PHADJ VBRT VBRTS
FLASH CONVERTER
(8 -BIT)
FLASH CONVERTER
(8 -BIT)
VARBS VARB
8
STROBE
8
VBRBS VBRB
L
A
T
C
H
E
S
8
ADATA
B
U
F
DCLK
F
E DCLK
R
L8
A BDATA
T
C
H
E
S
________________________________________________________________ Maxim Integrated Products 1
For the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
1 page  
500Msps, 8-Bit ADC with Track/Hold
____________________________Typical Operating Characteristics (continued)
(VEE = -5.2V, VCC = +5V, RL = 100Ω to -2V, VART, VBRT = 0.95V, VARB, VBRB = -0.95V, TA = +25°C, unless otherwise noted.)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
FFT PLOT
(fAIN = 251.4462MHz)
fCLK = 500MHz
SER = -44.5dB
NOISE FLOOR = -67.3dB
SPURIOUS = -58.2dB
25 50 75 100 125
(MHz)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
FFT PLOT
(fAIN = 10.4462MHz)
fCLK = 250MHz
SER = -47.2dB
NOISE FLOOR = -70.5dB
SPURIOUS = -61.8dB
12.5 25 37.5
(MHz)
50 62.5
EFFECTIVE BITS vs. ANALOG INPUT
FREQUENCY (fAIN)
(fCLK = 500MHz, VIN = 95% FS)
8
7
RECORD LENGTH = 512
6
0 50 100 150 200
fAIN (MHz)
250 300
EFFECTIVE BITS vs. CLOCK
FREQUENCY (fCLK)
(fAIN = 10.4462, VIN = 95% FS)
8
7
6
0 100 200 300 400 500 600
fCLK (MHz)
_______________________________________________________________________________________ 5
5 Page 
500Msps, 8-Bit ADC with Track/Hold
_______________Detailed Description
Converter Operation
The parallel or “flash” architecture used by the MAX101A
provides the fastest multibit conversion of all common
integrated ADC designs. The basic element of a flash, as
with all other ADC architectures, is the comparator, which
has a positive input, a negative input, and an output. If
the voltage at the positive input is higher than the nega-
tive input (connected to a reference), the output will be
high. If the positive input voltage is lower than the refer-
ence, the output will be low. A typical n-bit flash consists
of 2n - 1 comparators with negative inputs evenly spaced
at 1LSB increments from the bottom to the top of the ref-
erence ladder. For n = 8, there are 255 comparators.
For any input voltage, all the comparators with negative
inputs connected to the reference ladder below the
input voltage will have outputs of 1 and all comparators
with negative inputs above the input voltage will have
outputs of 0. Decode logic is provided to convert this
information into a parallel n-bit digital word (the output)
corresponding to the number of LSBs (minus 1) that the
input voltage is above the bottom of the ladder.
The comparators contain latch circuitry and are
clocked. This allows the comparators to function as
described previously when, for example, clock is low.
When clock goes high (samples) the comparator will
latch and hold its state until the clock goes low again.
The MAX101A uses a monolithic, dual-interleaved par-
allel quantizer chip with two separate 8-bit converters.
These converters deliver results to the A and B output
latches on alternate negative edges of the input clock.
Track/Hold
As with all ADCs, if the input waveform is changing
rapidly during the conversion, the effective bits and
SNR will decrease. The MAX101A has an internal
track/hold (T/H) that increases attainable effective-bits
performance and allows more accurate capture of ana-
log data at high conversion rates.
The internal T/H circuit provides two important circuit
functions for the MAX101A:
1) Its nominal voltage gain of 4 reduces the input dri-
ving signal to ±250mV differential (assuming a
±0.95V reference).
2) It provides a differential 50Ω input that allows easy
interface to the MAX101A.
Table 1. Output Mode Control
DIV10
DCLK*
(MHz)
MODE
DESCRIPTION
OPEN 250
Normal AData and BData valid on oppo-
Divide site DCLK edges (AData on rise,
by 2 BData on fall).
AData and BData valid on oppo-
Test site DCLK edges (AData on rise,
GND 50 Divide BData on fall). Data sampled at
by 10 input CLK rate but 4 out of every
5 samples discarded.
* Input clocks (CLK, CLK) = 500MHz for all above combinations. In
all modes, the output clock DCLK will be a 50% duty-cycle signal.
Data Flow
The MAX101A’s internal T/H amplifier samples the ana-
log input voltage for the ADC to convert. The T/H is split
into two sections that operate on alternate negative
clock edges. The input clock, CLK, is conditioned by
the T/H and fed to the A/D section. The output clock,
DCLK, used for output data timing, will be divided by 2
or 10 from the input clock (Table 1). This results in an
output data rate of 250Mbps on each output port in nor-
mal mode and 50Mbps in test mode. The differential
inputs, AIN+ and AIN-, are tracked continuously
between data samples. When a negative strobe edge is
sensed, one-half of the T/H goes into hold mode (Figure
4). When the strobe is low, the just-acquired sample is
presented to the ADC’s input comparators. Internal pro-
cessing of the sampled data takes an additional 15
clock cycles before it is available at the outputs, AData
and BData. See Figures 1–3 for timing.
__________Applications Information
Analog Input Ranges
Although the normal operating range is ±250mV, the
MAX101A can be operated with up to ±500mV on each
input with respect to ground. This extended input level
includes the analog signal and any DC common-mode
voltage.
To obtain full-scale digital output with differential
input drive, a nominal +250mV must be applied
between AIN+ and AIN-. That is, AIN+ = +125mV and
AIN- = -125mV (with no DC offset). Mid-scale digital
output code occurs when there is no voltage difference
across the analog inputs. Zero-scale digital output
code, with differential -250mV drive, occurs when AIN+
= -125mV and AIN- = +125mV. Table 2 shows how the
output of the converter stays at all ones (full scale)
when over-ranged or all zeros (zero scale) when under-
ranged.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet MAX101A.PDF ] | |
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