DataSheet.jp

MA7001 の電気的特性と機能

MA7001のメーカーはDynexです、この部品の機能は「Radiation Hard 512x9 Bit FIFO」です。


製品の詳細 ( Datasheet PDF )

部品番号 MA7001
部品説明 Radiation Hard 512x9 Bit FIFO
メーカ Dynex
ロゴ Dynex ロゴ 




このページの下部にプレビューとMA7001ダウンロード(pdfファイル)リンクがあります。

Total 15 pages

No Preview Available !

MA7001 Datasheet, MA7001 PDF,ピン配置, 機能
Replaces June 1999 version, DS3519-4.0
MAM7A0700011
Radiation Hard 512x9 Bit FIFO
DS3519-5.0 January 2000
The MA7001 512 x 9 FIFO is manufactured using Dynex
Semiconductor's CMOS-SOS high performance, radiation
hard, 3µm technology.
The Dynex Semiconductor Silicon-on-Sapphire process
provides significant advantages over bulk silicon substrate
technologies In addition to very good total dose hardness and
neutron hardness >1015n/cm2, the Dynex Semiconductor
technology provides very high transient gamma and single
event upset performance without compromising speed of
operation The Sapphire substrate also eliminates latch-up
giving greater flexibility of use in electrically severe
environments.
The MA7001 implements a First-ln First-Out algorithm that
reads and writes data on a first-in first-out basis. The dual-port
static RAM memory is organised as 512 words of 9 bits (8 bit
data and 1 bit for parity or control purposes).
Sequential read and write accesses are achieved using a
ring pointer architecture that requires no external addressing
information. Data is toggled in and out of the device by using
the WRITE (W) and READ (R) pins.
Full and Empty status flags prevent data overflow and
underflow. Expansion logic on the device allows for unlimited
expansion capability in both word size and depth. A
RETRANSMIT (RT) feature allows for reset of the read pointer
to its initial position to allow retransmission of data.
The device is designed for applications requiring
asynchronous and simultaneous read/write in multiprocessing
and rate buffering (sourcing and sinking data at different rates
eg. interfacing fast processors and slow peripherals).
FEATURES
s Radiation Hard CMOS-SOS Technology
s Fast Access Time 60ns Typical
s Single 5V Supply
s Inputs Fully TTL and CMOS Compatible
s -55°C to +125°C Operation
Figure 1: Block Diagram
1/15

1 Page





MA7001 pdf, ピン配列
AC CHARACTERISTICS
Characteristics apply to pre-radiation at TA = -55°C to +125°C, VDD = 5V ±10% and post
100kRad(Si) total dose radiation at TA = 25°C, VDD = 5V ±10%. GROUP A SUBGROUP 9, 10, 11.
Symbol Parameter
Min.
Max. Units
tRC
tA
tRR
tRPW
tRLZ
tDV
tRHZ
tWC
tWPW
tWR
tDS
tDH
tRSC
tRS
tRSR
tRTC
tRT
tRTR
tEFL
tREF
tRFF
tWEF
tWFF
tEFR
tRPI
tFFW
tWPI
Read Cycle Time
Access Time
Read Recovery Time
Read Pulse Width (Note 2)
Read Pulse Low to Data Bus at Low Z (Note 3)
Data Valid from Read Pulse High
Read Pulse High to Data Bus at High Z (Note 3)
Write Cycle Time
Write Pulse Width (Note 2)
Write Recovery Time
Data Setup Time
Data Hold Time
Reset Cycle Time (Note 3)
Reset Pulse Width (Note 2)
Reset Recovery Time (Note 3)
Retransmit Cycle Time (Note 3)
Retransmit Pulse Width (Note 2)
Retransmit Recovery Time (Note 3)
Reset to Empty Flag Low
Read Low to Empty Flag Low
Read High to Full Flag High
Write High to Empty Flag High
Write Low to Full Flag Low
EF High to Valid Read (Note 3)
Read Protect Indeterminant (Note 3)
FF High to Valid Wrlte (Note 3)
Write Protect Indeterminant (Note 3)
Notes:
1. Timings referenced as in A.C. Test Conditions, figure 5
2. Pulse wldths less than minimum values are not allowed
3. Values guaranteed by deslgn, not currently tested
110 -
- 100
25 -
85 -
10 -
20 -
- 30
100 -
80 -
20 -
40 -
10 -
100 -
80 -
20 -
100 -
80 -
20 -
- 100
- 90
- 70
- 70
- 90
10 -
- 35
10 -
- 35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 3b: AC Characteristics
MA7001
3/15


3Pages


MA7001 電子部品, 半導体
MA7001
SIGNAL DESCRIPTIONS
Reset (RS)
Reset occurs when RS is in a low state, setting both read and
write pointers to the first location in memory. Reset is required
prior to the first write. Both READ (R) and WRITE (W) signals
must be in high states during reset.
Read Enable (R):
Providing the EMPTY FLAG (EF) is not set, i.e. there is still
data to be read, a read cycle commences on the falling edge of
R, (see Figure 16). Data is read in a First-ln First-Out manner
independent of write operations. When reads are disabled
data outputs (Q0 - Q8) are in a high impedance state. Reading
the last available memory location sets the EMPTY FLAG
(EF), which is cleared following a write cycle.
As a WRITE operation is being performed to the last physical
memory location (511th) whilst the READ pointer is waiting at
the 510th physical location the FULL flag is activated for a
duration less than 20ns.
Note: The last physical location (511th) is accessed after 511
WRITE or READ operations after RESET.
Empty Flag (EF):
Following an initial RESET EF is active, becoming inactive
after the first write cycle, (see Figure 20). EF becomes active
once the read and write pointers are coincident following a
read cycle. Reading will not take place whilst EF is active, and
may only proceed once a write cycle has occured.
Write Enable (W):
Providing the FULL FLAG (FF) is not set, i.e. there exists at
least one memory location for writing, a write cycle
commences on the falling edge of (W), (see Figure 17). Data is
written into consecutive memory locations independent of read
operations on the rising edge of W. Data set up and hold times
are with respect to the rising edge of W.
Expansion In (Xl):
There are two possible modes of operation for the FIFO. One
with Xl grounded in which the device is in singledevice mode,
the other is a depth expension mode or daisy chain
configuration. In the latter mode Xl inputs come from
EXPANSION OUT (XO) outputs of the device preceding it in
the chain.
Expansion Out (XO):
In depth expansion mode XO from one device signals the next
device in the chain that the last location in its memory has been
accessed.
Full Flag (FF):
FF becomes active when the last available memory location
has been written to, (see Figure 18). In general, this occurs
whenever the write pointer coincides with the read pointer
following a write cycle. Writes are inhibited while FF is active,
and may only proceed after a read cycle has occured.
FF will go high tRFF after completion of a valid READ operation.
FF will go low tWFF from the beginning of a subsequent WRITE
operation, provided that a second READ has not been
completed. Writes beginning tFFW after FF goes high, are valid.
Writes beginning after FF goes low and ending more than tWPI
before FF goes high, are invalid (ignored). Writes beginning
less than twpl before FF goes high and less than tFFW later,
may or may not occur (be valid) depending on the internal flag
status (see Figure 19).
EF will go high tWEF after completion of a valid WRITE
operation. EF will again go low tREF from the beginning of a
subsequent READ operation, provided that a second WRITE
has not been completed. Reads beginning tEFR after EF goes
high, are valid. Reads begun after EF goes low and ending
more than tRPI before EF goes high, are invalid (ignored).
Reads beginning less than tRIP before EF goes high and less
than tEFR later, may or may not occur (be valid) depending on
the internal flag status (See Figure 21). If a Read to the last but
one physical location completes while the last location (511th)
is being written, the EF will not be activated. The next Read
should be activated after the last Write has completed.
First Load/Retransmit (FL/RT):
This is a dual purpose input depending on the mode of
operation of the device. In single device mode Xl = 0 data may
be retransmitted, i.e. it may be re-read. In depth expansion
mode FL signifies the first device in the chain. When RT is
pulsed low the read pointer is set to the first memory location.
The write pointer is unaffected. This feature is disabled in
depth expansion mode, and can only be applied when R and
W are inactive (See Figure 22).
Data Inputs (D0 - D8): Data inputs, 9 bit word, for write
operations.
Data Outputs (Q0 - Q8):
Data outputs, 9 bit word, for read operations. When R is
inactive these outputs are in a high impedance state.
If a Write to the last but one physical location completes while
the last location (511th) is being Read, the FF will not be
activated. The next Read should start after the last Write has
completed.
6/15

6 Page



ページ 合計 : 15 ページ
 
PDF
ダウンロード
[ MA7001 データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
MA700

Silicon epitaxial planar type

Panasonic
Panasonic
MA700

SCHOTTKY BARRIER DIODES

EIC
EIC
MA7000

Silicon planar type

Panasonic
Panasonic
MA7000

Silicon Planar Type

Panasonic
Panasonic


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap