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MC14011 の電気的特性と機能

MC14011のメーカーはMotorola Semiconductorsです、この部品の機能は「UB-Suffix Series COMS Gates」です。


製品の詳細 ( Datasheet PDF )

部品番号 MC14011
部品説明 UB-Suffix Series COMS Gates
メーカ Motorola Semiconductors
ロゴ Motorola Semiconductors ロゴ 




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MC14011 Datasheet, MC14011 PDF,ピン配置, 機能
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
UB-Suffix Series CMOS Gates
The UB Series logic gates are constructed with P and N channel
enhancement mode devices in a single monolithic structure (Complemen-
tary MOS). Their primary use is where low power dissipation and/or high
noise immunity is desired. The UB set of CMOS gates are inverting
non–buffered functions.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Linear and Oscillator Applications
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
Double Diode Protection on All Inputs
Pin–for–Pin Replacements for Corresponding CD4000 Series UB Suffix
Devices
LOGIC DIAGRAMS
MC14001UB
Quad 2–Input
NOR Gate
1
23
54
6
8
10
9
12
11
13
MC14012UB
Dual 4–Input
NAND Gate
2
3
1
4
5
9
10 13
11
12
NC = 6, 8
MC14002UB
Dual 4–Input
NOR Gate
2
3
41
5
9
10
13
11
12 NC = 6, 8
MC14011UB
Quad 2–Input
NAND Gate
1
3
2
5
4
6
8
10
9
12
11
13
MC14023UB
Triple 3–Input
NAND Gate
1
29
8
3
46
5
11
12 10
13
MC14025UB
Triple 3–Input
NOR Gate
1
2
8
3
4
5
11
12
13
9
6
10
VDD = PIN 14
VSS = PIN 7
FOR ALL DEVICES
MC14001UB
Quad 2-Input NOR Gate
MC14002UB
Dual 4-Input NOR Gate
MC14011UB
Quad 2-Input NAND Gate
MC14012UB
Dual 4-Input NAND Gate
MC14023UB
Triple 3-Input NAND Gate
MC14025UB
Triple 3-Input NOR Gate
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXUBCP
MC14XXXUBCL
MC14XXXUBD
Plastic
Ceramic
SOIC
TA = – 55° to 125°C for all packages.
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
v voperation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
REV 3
1/94
©MMCot1or4o0la0, I1nUc.B1995
18
MOTOROLA CMOS LOGIC DATA

1 Page





MC14011 pdf, ピン配列
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎELECTRICAL CHARACTERISTICS (VoltagesReferencedtoVSS)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎCharacteristic
VDD
Symbol Vdc
– 55_C
Min Max
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin= VDDor0
“0” Level VOL
5.0
0.05
10 — 0.05
15 — 0.05
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVin = 0 or VDD
“1” Level VOH
5.0 4.95
10 9.95
15 14.95
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Voltage
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 4.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 9.0 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 1.0 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VO = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎOutput Drive Current
(VOH = 2.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 4.6 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
“0” Level VIL
“1” Level
IIH
Source
IOH
5.0 — 1.0
10 — 2.0
15 — 2.5
5.0 4.0
10 8.0
15 12.5
5.0 – 1.2
5.0 – 0.25
10 – 0.62
15 – 1.8
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.4 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 0.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(VOL = 1.5 Vdc)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎInput Capacitance
(Vin = 0)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎQuiescent Current
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ(Per Package)
Sink IOL
Iin
Cin
IDD
5.0 0.64
10 1.6
15 4.2
15 — ± 0.1
—— —
5.0 — 0.25
10 — 0.5
15 — 1.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎTotal Supply Current**†
(Dynamic plus Quiescent,
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎPer GateCL=50pF)
IT 5.0
10
15
Min
4.95
9.95
14.95
25_C
Typ #
0
0
0
5.0
10
15
Max
0.05
0.05
0.05
— 2.25
— 4.50
— 6.75
4.0 2.75
8.0 5.50
12.5 8.25
1.0
2.0
2.5
– 1.0
– 0.2
– 0.5
– 1.5
0.51
1.3
3.4
– 1.7
– 0.36
– 0.9
– 3.5
0.88
2.25
8.8
± 0.00001
5.0
± 0.1
7.5
— 0.0005 0.25
0.0010
0.5
0.0015
1.0
IT = (0.3 µA/kHz) f + IDD/N
IT = (0.6 µA/kHz) f + IDD/N
IT = (0.8 µA/kHz) f + IDD/N
125_C
Min Max
— 0.05
— 0.05
— 0.05
4.95
9.95
14.95
— 1.0
— 2.0
— 2.5
4.0 —
8.0 —
12.5 —
– 0.7
– 0.14
– 0.35
– 1.1
0.36
0.9
2.4
± 1.0
Unit
Vdc
Vdc
Vdc
Vdc
mAdc
mAdc
µAdc
pF
— 7.5 µAdc
— 15
— 30
µAdc
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
** The formulas given are for the typical characteristics only at 25_C.
†To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µH (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.001 x the number of exercised gates per
package.
MC14001UB
20
MOTOROLA CMOS LOGIC DATA


3Pages


MC14011 電子部品, 半導体
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
ISSUE Y
–A–
14 9
–B–
17
CL
–T–
SEATING
PLANE
F
GN
D 14 PL
0.25 (0.010) M T A S
K
M
J 14 PL
0.25 (0.010) M T B S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION F MAY NARROW TO 0.76 (0.030)
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.750 0.785 19.05 19.94
B 0.245 0.280 6.23 7.11
C 0.155 0.200 3.94 5.08
D 0.015 0.020 0.39 0.50
F 0.055 0.065 1.40 1.65
G 0.100 BSC
2.54 BSC
J 0.008 0.015 0.21 0.38
K 0.125 0.170 3.18 4.31
L 0.300 BSC
7.62 BSC
M 0_ 15_ 0_ 15_
N 0.020 0.040 0.51 1.01
14
1
A
F
HG
8
B
7
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
C
N
SEATING
PLANE
D
K
L
J
M
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A 0.715 0.770 18.16 19.56
B 0.240 0.260 6.10 6.60
C 0.145 0.185 3.69 4.69
D 0.015 0.021 0.38 0.53
F 0.040 0.070 1.02 1.78
G 0.100 BSC
2.54 BSC
H 0.052 0.095 1.32 2.41
J 0.008 0.015 0.20 0.38
K 0.115 0.135 2.92 3.43
L 0.300 BSC
7.62 BSC
M 0_ 10_ 0_ 10_
N 0.015 0.039 0.39 1.01
MOTOROLA CMOS LOGIC DATA
MC14001UB
23

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