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PDF MC10EP016 Data sheet ( Hoja de datos )
| Número de pieza | MC10EP016 | |
| Descripción | 3.3V / 5VECL 8-Bit Synchronous Binary Up Counter | |
| Fabricantes | ON Semiconductor | |
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MC10EP016, MC100EP016
3.3V / 5V ECL 8-Bit
Synchronous Binary Up
Counter
Description
The MC10/100EP016 is a high-speed synchronous, presettable,
cascadeable 8-bit binary counter. Architecture and operation are the
same as the MC10E016 in the ECLinPS™ family.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all-one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non-cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
Features
•ă500 ps Typical Propagation Delay
•ăPECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
•ăNECL Mode Operating Range: VCC = 0 V
with VEE = -3.0 V to -5.5 V
•ăOpen Input Default State
•ăSafety Clamp on Inputs
•ăInternal TC Feedback (Gated)
•ăAddition of COUT and COUT
•ă8-Bit
•ăDifferential Clock Input
•ăVBB Output
•ăFully Synchronous Counting and TC Generation
•ăAsynchronous Master Reset
•ăPb-Free Packages are Available*
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MARKING
DIAGRAMS*
LQFP-32
FA SUFFIX
CASE 873A
MCxxx
EP016
AWLYYWWG
1 32
QFN32
MN SUFFIX
CASE 488AM
1
MCxxx
EP016
AWLYYWWG
G
xxx = 10 or 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©Ă Semiconductor Components Industries, LLC, 2007
August, 2007 - Rev. 12
1
Publication Order Number:
MC10EP016/D
1 page  
MC10EP016, MC100EP016
Table 4. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
LQFP-32
QFN-32
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
N/A
> 2 kV
> 100 V
> 2 kV
Pb Pkg
Pb-Free Pkg
Level 2
N/A
Level 2
Level 1
UL 94 V-0 @ 0.125 in
897 Devices
Table 5. MAXIMUM RATINGS)
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
6V
-6 V
6V
-6 V
50 mA
100 mA
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
32 LQFP
32 LQFP
± 0.5
-40 to +85
-65 to +150
80
55
mA
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case) Standard Board
32 LQFP
qJA Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
QFN-32
QFN-32
12 to 17
31
27
°C/W
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case) (Note 2)
QFN-32
12 °C/W
Tsol Wave Solder
Pb
Pb-Free
265 °C
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with y8 filled thermal vias under exposed pad.
http://onsemi.com
5
5 Page 
MC10EP016, MC100EP016
Applications Information (continued)
HL L L HHHH
P7 P6 P5 P4 P3 P2 P1 P0
H PE
L CE
H TCLD
TC
CLK COUT
CLK COUT
Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Figure 5. Mod 2 to 256 Programmable Divider
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn's = 256 - 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 5
will result in the waveforms of Figure 6. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
Table 13. PRESET VALUES FOR VARIOUS DIVIDE
RATIOS
Divide
Ratio
Preset Data Inputs
P7 P6 P5 P4 P3 P2 P1 P0
2 HH H H H H H L
3 HH H H H H L H
4 HH H H H H L L
5 HH H H H L H H
w w• • • • • • •
w •• • • • • • •
112 H L L H L L L L
113 H L L L H H H H
114 H L L L H H H L
• •• • • • • • •
• •• • • • • • •
254 L L L L L L H L
255 L L L L L L L H
256 L L L L L L L L
A single EP016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed multiple EP016s can be cascaded in a manner similar
to that already discussed. When EP016s are cascaded to
build larger dividers the TCLD pin will no longer provide a
means for loading on terminal count. Because one does not
want to reload the counters until all of the devices in the
chain have reached terminal count, external gating of the TC
pins must be used for multiple EP016 divider chains.
CLK
PE
Load
1001 0000 1001 0001 1111 1100 1111 1101
•••
1111 1110 1111 1111
Load
•••
•••
TC DIVIDE BY 113
Figure 6. Divide by 113 EP016 Programmable Divider Waveforms
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11
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| PDF Descargar | [ Datasheet MC10EP016.PDF ] | |
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