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MC100EP33のメーカーはON Semiconductorです、この部品の機能は「3.3V 5VECL / 4 Divider」です。 |
部品番号 | MC100EP33 |
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部品説明 | 3.3V 5VECL / 4 Divider | ||
メーカ | ON Semiconductor | ||
ロゴ | |||
このページの下部にプレビューとMC100EP33ダウンロード(pdfファイル)リンクがあります。 Total 11 pages
MC10EP33, MC100EP33
3.3 V/5 V ECL B4 Divider
Description
The MC10/100EP33 is an integrated B4 divider. The differential
clock inputs.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The reset pin is asynchronous and is asserted on the rising edge.
Upon powerup, the internal flip-flops will attain a random state; the
reset allows for the synchronization of multiple EP33’s in a system.
The 100 Series contains temperature compensation.
Features
• 320 ps Propagation Delay
• Maximum Frequency = > 4 GHz Typical
• PECL Mode Operating Range:
VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• VBB Output
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
8
1
8
1
SOIC−8 NB
TSSOP−8
DFN8
D SUFFIX
DT SUFFIX MN SUFFIX
CASE 751−07 CASE 948R−02 CASE 506AA
MARKING DIAGRAMS*
8
HEP64
ALYW
G
1
8
HP64
ALYWG
G
1
14
8
KEP64
ALYW
G
1
SOIC−8 NB
8
KP64
ALYWG
G
1
TSSOP−8
14
DFN8
H = MC10 A = Assembly Location
K = MC100 L = Wafer Lot
5Q = MC10 Y = Year
3L = MC100 W = Work Week
M = Date Code
G = Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
August, 2016 − Rev. 11
1
Publication Order Number:
MC10EP33/D
1 Page MC10EP33, MC100EP33
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply
VEE NECL Mode Power Supply
VI PECL Mode Input Voltage
NECL Mode Input Voltage
Iout Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI ≤ VCC
VI ≥ VEE
6V
−6 V
6V
−6
50 mA
100
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
±0.5
−40 to +85
−65 to +150
190
130
mA
°C
°C
°C/W
qJC Thermal Resistance (Junction-to-Case)
Standard Board
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
TSSOP−8
TSSOP−8
41 to 44
185
140
°C/W
°C/W
qJC Thermal Resistance (Junction-to-Case)
Standard Board
TSSOP−8
Tsol Wave Solder
< 2 to 3 sec @ 248°C
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN8
DFN8
41 to 44
265
129
84
°C/W
°C
°C/W
Tsol Wave Solder (Pb-Free)
< 2 to 3 sec @ 260°C
265 °C
qJC Thermal Resistance (Junction-to-Case)
(Note 2)
DFN8
35 to 40
°C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
Table 5. 10EP DC CHARACTERISTICS, PECL (VCC = 3.3 V, VEE = 0 V (Note 1))
−40°C
Symbol
Characteristic
Min Typ Max Min
IEE Power Supply Current
18 26 40 18
VOH Output HIGH Voltage (Note 2)
2165 2290 2415 2230
VOL Output LOW Voltage (Note 2)
VIH Input HIGH Voltage (Single-Ended)
VIL Input LOW Voltage (Single-Ended)
1365
2090
1365
1490
1615
2415
1690
1430
2155
1430
VBB Output Voltage Reference
1790 1890 1990 1855
VIHCMR Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
2.0
3.3 2.0
25°C
Typ
26
2355
1555
1955
Max
40
2480
1680
2480
1755
2055
3.3
Min
18
2290
1490
2215
1490
1915
2.0
85°C
Typ
26
2415
1615
2015
Max
40
2540
1740
2540
1815
2115
3.3
Unit
mA
mV
mV
mV
mV
mV
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to −2.2 V.
2. All loading with 50 W to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
www.onsemi.com
3
3Pages MC10EP33, MC100EP33
Table 10. 100EP DC CHARACTERISTICS, NECL (VCC = 0 V; VEE = −5.5 V to −3.0 V (Note 1))
−40°C
25°C
85°C
Symbol
IEE
VOH
VOL
VIH
VIL
VBB
VIHCMR
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Output LOW Voltage (Note 2)
Input HIGH Voltage (Single-Ended)
Input LOW Voltage (Single-Ended)
Output Voltage Reference
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
Min Typ
18 26
−1145 −1020
−1945 −1820
−1225
−1945
−1525 −1425
VEE+2.0
Max
40
−895
−1695
−880
−1625
−1325
0.0
Min Typ
23 26
−1145 −1020
−1945 −1820
−1225
−1945
−1525 −1425
VEE+2.0
Max
45
−895
−1695
−880
−1625
−1325
0.0
Min Typ
23 26
−1145 −1020
−1945 −1820
−1225
−1945
−1525 −1425
VEE+2.0
Max
45
−895
−1695
−880
−1625
−1325
0.0
Unit
mA
mV
mV
mV
mV
mV
V
IIH Input HIGH Current
150 150 150 mA
IIL Input LOW Current
0.5 0.5 0.5 mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC.
2. All loading with 50 W to VCC − 2.0 V.
3. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
Table 11. AC CHARACTERISTICS (VCC = 0 V; VEE = −3.0 V to −5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
VOPP Output Voltage Amplitude (See Figure 4)
mV
fin < 4.0 GHz
700 700 700
fin < 4.5 GHz
600 600 600
tPLH,
tPHL
Propagation Delay to
CLK/Q
Output Differential
RESET/Q
ps
300 380 440 300 380 440 320 400 460
370 420 470 370 420 470 400 450 500
tRR
tPW
tJITTER
VPP
Set/Rest Recovery
Minimum Pulse width
Random Clock Jitter (RMS)
Input Voltage Swing
(Differential Configuration)
RESET
150
550
150
100 200
480 550
0.2 2
800 1200 150
100 200
480 550
0.2 2
800 1200 150
100 ps
480 ps
0.2 2 ps
800 1200 mV
ttrf
Output Rise/Fall Times
Q, Q (20%−80%)
ps
90 170 200 100 180 250 120 200 280
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
www.onsemi.com
6
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PDF ダウンロード | [ MC100EP33 データシート.PDF ] |
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