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PDF LMX3162 Data sheet ( Hoja de datos )
| Número de pieza | LMX3162 | |
| Descripción | Single Chip Radio Transceiver | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de LMX3162 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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PRELIMINARY
March 2000
LMX3162
Single Chip Radio Transceiver
General Description
The LMX3162 Single Chip Radio Transceiver is a monolithic,
integrated radio transceiver optimized for use in ISM 2.45
GHz wireless systems. It is fabricated using National’s ABiC
V BiCMOS process (fT = 18 GHz).
The LMX3162 contains phase locked loop (PLL), transmit
and receive functions. The 1.3 GHz PLL is shared between
transmit and receive sections. The transmitter includes a fre-
quency doubler, and a high frequency buffer. The receiver
consists of a 2.5 GHz low noise mixer, an intermediate fre-
quency (IF) amplifier, a high gain limiting amplifier, a fre-
quency discriminator, a received signal strength indicator
(RSSI), and an analog DC compensation loop. The PLL,
doubler, and buffers can be used to implement open loop
modulation along with an external VCO and loop filter. The
circuit features on-chip voltage regulation to allow supply
voltages ranging from 3.0V to 5.5V. Two additional voltage
regulators provide a stable supply source to external dis-
crete stages in the Tx and Rx chains.
The IF amplifier, high gain limiting amplifier, and discrimina-
tor are optimized for 110 MHz operation, with a total IF gain
of 85 dB. The single conversion receiver architecture pro-
vides a low cost, high performance solution for communica-
tions systems. The RSSI output may be used for channel
quality monitoring.
The Single Chip Radio Transceiver is available in a 48-pin
7mm X 7mm X 1.4mm PQFP surface mount plastic pack-
age.
Features
n Single chip solution for ISM 2.45 GHz RF transceiver
n System RF sensitivity to −93 dBm; RSSI sensitivity to
−100 dBm
n Two regulated voltage outputs for discrete amplifiers
n High gain (85 dB) intermediate frequency strip
n Allows unregulated 3.0V–5.5V supply voltage
n Power down mode for increased current savings
n System noise figure 6.5 dB (typ)
Applications
n ISM 2.45 GHz frequency band wireless systems
n Personal wireless communications (PCS/PCN)
n Wireless local area networks (WLANs)
n Other wireless communications systems
Block Diagram
MICROWIRE™ is a trademark of National Semiconductor Corporation.
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2000 National Semiconductor Corporation DS100929
DS100929-1
www.national.com
1 page  
Pin Descriptions (Continued)
Pin No.
32
Pin Name
DC COMPIN
I/O Description
I Input to DC compensation circuit.
33
DISCOUT
O Demodulated output of discriminator.
34
GND
— Ground.
35 VCC — Power supply for the discriminator circuit.
36
QUADIN
I Quadrature input for tank circuit.
37 VCC — Power supply for limiter output stage.
38
GND
— Ground.
39 VCC — Power supply for limiter gain stages.
40
GND
— Ground.
41 VCC — Power supply for IF amplifier gain stages.
42
LIMIN
I IF input to the limiter.
43
GND
— Ground.
44
IFOUT
O IF output from IF amplifier.
45 VCC — Power supply for IF amplifier output.
46
GND
— Ground.
5
www.national.com
5 Page 
Typical Performance Characteristics (Continued)
SSB Mixer Noise Figure vs RFIN Frequency
SSB Mixer Noise Figure vs FIN Power
TX Power Out vs FIN Power
DS100929-47
TX Power Out vs FIN Frequency
DS100929-48
DS100929-49
AC Timing Characteristics
DS100929-50
Serial Data Input Timing
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has
an skew rate of 0.6 V / ns.
Notes: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
11
DS100929-3
www.national.com
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet LMX3162.PDF ] | |
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