OZ968 データシート ( High-Efficiency Inverter Controller )

部品番号

OZ968

部品説明

High-Efficiency Inverter Controller

メーカ

ETC

ロゴ

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OZ968

SMBus Smart Inverter Controller

FEATURES

GENERAL DESCRIPTION

• Single-stage power conversion

• Constant frequency design eliminates inter-

ference with LCDs

• Built-in open-lamp protection and short-

circuit protection

• Reliable 2-winding transformer design elimi-

nates arcing failures and the need for fold-

back wiring

• 32-level dimming and 256-level contrast

control via SMBus

• High efficiency, 90% typical

• Supports both floating secondary and

grounded secondary designs

ORDERING INFORMATION

OZ968G - 16-pin plastic SOP

The OZ968 is a unique single-stage, high-

efficiency, CCFL backlight controller. It drives a

zero-voltage-switching circuit and provides a

near sinusoidal output voltage and current wave-

forms for a CCFL backlight. Typical operating

frequency ranges from 30KHz to 100KHz. These

advances drive the OZ968 beyond comparable

conventional inverter designs with two power

conversion stages (one operates at a variable

frequency, the other at a constant frequency).

Operating in a PWM push-pull drive, the trans-

former in an OZ968 backlight inverter requires

only one primary winding and one secondary

winding. The secondary winding requires no fold-

back treatment.

The OZ968 supports a bi-directional, two-wire

bus, data transmission protocol to control dim-

ming (32 levels) and contrast (256 levels). Sup-

ply current is 1mA in active mode, 150µA in

standby mode.

TYPICAL APPLICATION CIRCUIT

20V

SMBCLCK

SMBDATA

ENABLE

CONTRAST

0.47u

1 FB

2 CMP

0.1u

3 SST

4 ADJ

OZ968

VDD 16

SCP 15

VSEQ 14

SMBD 13

0.1u

5 CNT

SMBC 12

120k

220p

6 RT

7 CT

8 GND

OVP 11

PDR 10

NDR 9

10k

The OZ968 is available in a 16-pin SOP pack-

age. It is specified over the commercial tempera-

ture range 0oC to +70oC.

47u/

25v

3.3k

3904

1:40

22p/3KV

2.2k

3904

200k

3906

Si4559EY/P

4.7u

1N4148

Si4559EY/

R5 R7

10k

0.1ohm

R10

100k

CCFL

1N4148

Figure 1. Typical Application Circuit

06/15/00

OZ968-SF-1.5

Page 1

U.S. Patent #5,619,402

1 Page

PIN CONFIGURATION

OZ968

Pin No.

Name

CMP

SST

ADJ

CNT

GND

NDR

PDR

OVP

SMBC

SMBD

VSEQ

SCP

VDD

Description

Current sense feedback.

Compensation for the current sense feedback.

Soft start in two steps. Two-interval current sources of 50µA and 0.6µA

provide 1:26.6 ratio between the two time intervals of soft start. Connect a

capacitor between this pin and the ground to adjust the soft-start timing.

The output of the brightness D/A converter. The brightness has 32 adjust-

able levels. The default range is between 0.9V to 2.5V.

The output of the contrast D/A converter. The contrast has 256 levels from

0.8V to 2.8 V (8mV per step). This output has a current capability of up to

2mA.

Timing resistor.

Timing capacitor. CT and RT set the clock frequency. Fs = 1.60 / (RT * CT).

Ground.

Gate drive output for the N-MOSFET.

Gate drive output for the P-MOSFET.

Over-voltage protection sense input.

SMBus Clock Input/Output

SMBus Data Input/Output.

Vee power sequence input.

Short-circuit protection sense input.

Supply voltage input.

ABSOLUTE MAXIMUM RATINGS

VDD

GND

Storage temp.

Operating temp.

Operating junction temp.

7.0 V

+/- 0.3 V

-55 to 150 oC

0 to 70 oC

150 oC

Logic inputs

RECOMMENDED OPERATING RANGE

VDD

Fosc

4.75 V to 5.25 V

30 KHz to 100 KHz

Rt 50 K to 150 K

-0.3 V to VDD+0.3 V

OZ968-SF-1.5

Page 3

3Pages

PACKAGE INFORMATION

SOP-16

PACKAGE

OZ968

DIM

INCHES

MILLIMETERS

MIN MAX MIN MAX

A 0.0532 0.0688 1.35 1.75

A1 0.0040 0.0098 0.10 0.25

B 0.013 0.020 0.33 0.51

C 0.0075 0.0098 0.19 0.25

D 0.3859 0.3937 9.80 10.00

E 0.1497 0.1574 3.80 4.00

e 0.050 BCS. 1.27 BCS.

H 0.2284 0.2440 5.80 6.20

L 0.016 0.050 0.40 1.27

α 0° 8° 0° 8°

OZ968-SF-1.5

Page 6

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