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IA64250-PLC68M の電気的特性と機能

IA64250-PLC68MのメーカーはInnovASICです、この部品の機能は「Histogram/Hough Transform Processor」です。


製品の詳細 ( Datasheet PDF )

部品番号 IA64250-PLC68M
部品説明 Histogram/Hough Transform Processor
メーカ InnovASIC
ロゴ InnovASIC ロゴ 




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IA64250-PLC68M Datasheet, IA64250-PLC68M PDF,ピン配置, 機能
IA64250
Histogram/Hough Transform Processor
FEATURES
Histogram and Hough Transform Calculation
Data Sheet
As of Production Ver. 01
Four 512 X 9 Look-up Tables Provided to Perform User-defined Point-wise
Transformations
Real-time Histogram Equalization
High Data Rates
512 X 24 Accumulation RAM
Pixel Location Function
The IA64250 is a "plug-and-play" drop-in replacement for the original LSI® L64250. This replacement IC
has been developed using innovASIC’s MILESTM, or Managed IC Lifetime Extension System, cloning
technology. This technology produces replacement ICs far more complex than "emulation" while ensuring
they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even
as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the
"undocumented features" are duplicated. This data sheet documents all necessary engineering information
about the IA64250 including functional and I/O descriptions, electrical characteristics, and applicable timing.
Package Pinout for 68 PLCC PACKAGE:
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 1 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184

1 Page





IA64250-PLC68M pdf, ピン配列
IA64250
Histogram/Hough Transform Processor
BLOCK DIAGRAM:
Data Sheet
As of Production Ver. 01
Figure 1
MOD_RAMDATA
24
SYNC
AT
REGADR
6
STARTIO_N
RAMADDR 9
RAMDATA 24
HCLR 2
RESETFP
DI
9
CLOCK
IODV
CONTROLLER
SAT
SEL 4
LUT 2
LUTADDR 9
LUTDATA 9
ACC RAM
512 X 24
24
CLOCK
ADDER
24
SYNC
24
SHIFT
DV
LUT RAM
4 X 512 X 9
CLOCK
LUTOUT
9
ADDER
10
SHIFT
9
9
CI
9
RESET
9
CLOCK
FP
COUNTER
OUT_SEL
2
CY
CLOCK
RY
CX
CLOCK
RX
Y
COUNTER
X
COUNTER
9
Y
X
9
CI
AT
REGADR
MARKER MODE
MEMORY
WE_N
DO
9
OUT_SEL
VDO
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 3 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184


3Pages


IA64250-PLC68M 電子部品, 半導体
IA64250
Histogram/Hough Transform Processor
Data Sheet
As of Production Ver. 01
INITIALIZATION MODE:
Initialization defines the operation of the IA64250. The mode and marker memories store
66 nine-bit words that define the operation of the part and contain marker information. The
REGADR input is used to select the proper register. Data is written over the CI bus and
read on the DO bus. The AT pin controls whether data is a mode word or a marker. When
AT is low, the data written is mode information, which is stored in the mode registers
contained in the controller block. When AT is high, the data is a marker, and is stored in the
marker memory. To prevent erroneous operation STARTIOn should be high, and IODV
and DV should be low during initialization.
Mode Register Table:
A REGA R/ BIT LOCATION
T DR
W
W ci0 ci1 ci2
R do0 do1 do2
00
W sel0 sel1 sel2
01
W fn0 fn1 Eq
ci3 ci4 ci5
do3 do4 do5
sel3 lut0 lut1
io0 io1 hclr0
ci6
do6
sh1
hclr1
ci7 ci8
do7 do8
sat TESTn
func pdwn
Marker Memory Table:
AT REGADR
10
11
12
13
R/W
R
R
R
R
CONTENTS
GREY LEVEL OF MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 0-8
MAXIMUM ACC COUNT BITS 9-17
MAXIMUM ACC COUNT BITS 18-23*
1 16
1 17
1 18
1 19
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
W TEST MODE, DO NOT ACCESS
1 32
1 33
1 34
1 35
R/W
R/W
R/W
R/W
R/W MARKER 0 GREY LEVEL BITS 0-8
R/W MARKER 0 ACC COUNT BITS 0-8
R/W MARKER 0 ACC COUNT BITS 9-17
R/W MARKER 0 ACC COUNT BITS 18-23*
1 36
R/W
R/W MARKER 1 GREY LEVEL BITS 0-8
1 37
R/W
R/W MARKER 1 ACC COUNT BITS 0-8
1 38
R/W
R/W MARKER 1 ACC COUNT BITS 9-17
1 39
R/W
R/W MARKER 1 ACC COUNT BITS 18-23*
.
.
.
1 56
R/W
R/W MARKER 6 GREY LEVEL BITS 0-8
1 57
R/W
R/W MARKER 6 ACC COUNT BITS 0-8
1 58
R/W
R/W MARKER 6 ACC COUNT BITS 9-17
1 59
R/W
R/W MARKER 6 ACC COUNT BITS 18-23*
*ACC COUNT BIT 18-23 APPEARS ON BIT LOCATION 0-5 RESPECTIVELY
Copyright © 2000
innovASIC
The End of Obsolescence
ENG211001219-01
Page 6 of 21
www.innovasic.com
Customer Support:
1-888 -824-4184

6 Page



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部品番号部品説明メーカ
IA64250-PLC68M

Histogram/Hough Transform Processor

InnovASIC
InnovASIC


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