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PDF IA63484-PLC68I Data sheet ( Hoja de datos )
| Número de pieza | IA63484-PLC68I | |
| Descripción | Advanced CRT Controller | |
| Fabricantes | InnovASIC | |
| Logotipo |  |
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IA63484
Advanced CRT Controller
Preliminary Data Sheet
FEATURES
innovASIC
• High-speed graphics
- Drawing rate: 200 ns/pixel max (color drawing)
- Commands: 38 commands including 23 graphic drawing commands:
Dot, Line, Rectangle, Poly-line, Polygon, Circle, Ellipse, Paint, Copy, etc.
- Colors: 16 bits/word: 1,2,4,8,16 bits/pix el (5 types) monochrome to 64k colors max
- Pattern RAM: 32 bytes
- Converts logical X-Y coordinate to physical address
- Color operation and conditional drawing
- Drawing area control for hardware clipping and hitting
• Large frame-memory space
- Maximum 2 Mbytes graphic memory and 128 kbytes character memory separate from
MPU memory.
- Maximum Resolution: 4096 x 4096 pixels (1 bit/pixel mode)
• CRT display control
- Split Screens: three displays and one window
- Zoom: 1 to 16 times
- Scroll: vertical and horizontal
• Interleaved access mode for flashless display and superimposition
• External synchronization between ARTCs or between ACRTC and external device (TV system
or other controller.
• DMA interface
• Two programmable cursors
• Three Scan modes
- Non-interlaced
- Interlace sync
- Interlace sync and video
• Interrupt request to MPU
• 256 characters/line 32 raster/ line, 4096 rasters/screen
• Maximum clock frequency: 20MHz
• CMOS, single +5V power supply
The IA63484 is a "plug-and-play" drop-in replacement for the original Hitachi© HD63484. This
replacement IC has been developed using innovASIC’s MILESTM, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex
than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the
design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies
the clone against the original IC so that even the "undocumented features" are duplicated. This data
sheet documents all necessary engineering information about the IA63484 including functional and
I/O descriptions, electrical characteristics, and applicable timing.
Copyright © 2003
innov ASIC
The End of Obsolescence™
ENG 21101041201
Page 1 of 32
www.innovasic.com
Customer Support:
1−888−824−4184
1 page  
IA63484
Advanced CRT Controller
Figure 2: IA63484 Block Diagram
res_n
Preliminary Data Sheet
dreq_n
dack_n
done_n
irq_n
DMA
Control
Unit
Interrupt
Control
Unit
Register
Address
Data
Drawing
Processor
20
16
draw_adrs[19:0]
draw_data[15:0]
draw_en
write
16
d[15:0]
cs_n
rs_n
rw_n
dtack_n
MPU
Interface
23 25
V cc V SS
disp_adrs[19:0]
Display
Processor
20
15
raster_adrs[4:0]
chr_int
ccud
lpstb
2
Timing
Processor 2
gcud[1:0]
hsync
vsync
exsync
disp[1:0]
m_cyc
as
clk2
16
4
CRT
Interface
2
2
draw_n
mrd
mad[15:0]
ma19_16_ra[3:0]
ra4
chr
lpstb
cud1_n, cud2_n
hsync_n
vsync_n
exsync_n
disp1_n, disp2_n
mcyc
as_n
clk_2
IA63484 System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The IA63484 uses separate host MPU and frame buffer interfaces. This allows the IA63484 full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
IA63484. A related benefit is that a large frame buffer (2 MB for each IA63484) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The IA63484 can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the IA63484. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the IA63484 can be handled under MPU software control.
While both IA63484 bus interfaces (host MPU and frame buffer) are 16 bits wide, the IA63484 also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
Copyright © 2003
innov ASIC
The End of Obsolescence™
ENG 21101041201
Page 5 of 32
www.innovasic.com
Customer Support:
1−888−824−4184
5 Page 
IA63484
Advanced CRT Controller
Preliminary Data Sheet
In Interleaved Access Mode (dual access mode 0), display cycles and drawing cycles are interleaved.
A display or drawing cycle is defined as four cycles of clk_2.
• During the first clk_2 cycle, the IA63484 outputs the frame buffer display address.
• During the second clk_2 cycle, the display data is output from the frame buffer.
• During the third clk_2, the IA63484 outputs the frame buffer drawing address.
• During the fourth clk_2 cycle, the IA63484 reads or writes the drawing data.
In Superimposed Access Mode (dual access mode 1), two separate logical screens are accessed during
each display cycle. The display cycle is defined as four clk_2 cycles. If the third and fourth cycles are
not used for window display, they can be used for drawing; similar to the Interleaved Mode.
• During the first clk_2 cycle, the IA63484 outputs the background screen frame buffer address.
• During the second clk_2 cycle, the background screen displays data.
• During the third clk_2 cycle, the IA63484 outputs the window screen frame buffer address or
the drawing frame buffer address.
• During the fourth clk_2 cycle, the IA63484 reads (display or drawing) or writes (drawing) the
window screen display or drawing data.
Graphic Address Increment (GAI) Mode:
The IA63484 can be programmed to control the graphic display address in one of six ways, by
incrementing by 1, 2, 4, 8, and 16 words, 1 word every two display cycles, and no increment. Setting
GAI to increment by 2, 4, 8, or 16 words per display cycle achieves 2, 4, 8, or 16 times the video data
rate corresponding to GAI = 1. This allows the number of bits/logical pixel and logical pixel
resolution to be increased while meeting the clk_2 maximum frequency constraint.
When the frame buffer memory uses dynamic RAMs (DRAMs), the IA63484 automatically provides
DRAM refresh addressing.
During hsync_n low, the IA63484 outputs the values of an 8-bit DRAM refresh counter on the
multiplexed frame buffer address and data bus mad[15:0]. The counter is decremented on each
frame buffer access. The refresh address pin assignment (mad[15:0]) depends on the GAI mode.
The remaining mad and ma19_16_ra outputs not used for refresh addressing are cleared to a low
value.
Table 1: GAI and DRAM Refresh Addressing
Address Increment Mode
+1 (GAI = 000)
+2 (GAI = 001)
+4 (GAI = 010)
+8 (GAI = 011)
+16 (GAI = 100)
+0 (GAI = 101)
+1/2 (GAI = 11X)
Refresh Address Output Terminal
mad[7:0]
mad[8:1]
mad[9:2]
mad[10:3]
mad[11:4]
mad[7:0]
mad[7:0]
Copyright © 2003
innov ASIC
The End of Obsolescence™
ENG 21101041201
Page 11 of 32
www.innovasic.com
Customer Support:
1−888−824−4184
11 Page | ||
| Páginas | Total 32 Páginas | |
| PDF Descargar | [ Datasheet IA63484-PLC68I.PDF ] | |
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