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HYS72V32300GR-75-DのメーカーはInfineonです、この部品の機能は「PC133 Registered SDRAM-Modules」です。 |
部品番号 | HYS72V32300GR-75-D |
| |
部品説明 | PC133 Registered SDRAM-Modules | ||
メーカ | Infineon | ||
ロゴ | |||
このページの下部にプレビューとHYS72V32300GR-75-Dダウンロード(pdfファイル)リンクがあります。 Total 22 pages
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC133 1 GByte Module
PC133 2 GByte Module
• 168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• One bank 16M × 72, 32M x 72, 64M × 72and
128M x 72, two bank 128M × 72 and
256M x 72 organization
• Optimized for ECC applications with very low
input capacitances
• JEDEC standard Synchronous DRAMs
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
• Single + 3.3 V (± 0.3 V) power supply
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
• Card Size: 133.35 mm × 38.10 / 43.18 mm
with Gold contact pads and max. 4.00 / 6.80
mm thickness (JEDEC MO-161)
• These modules all fully compatible with the
current industry standard PC133 and PC100
specifications
• Performance:
speed grade
-7 -7.5 Unit
fCK Clock Frequency (max.) @ CL = 3 133 133 MHz
tCK Clock Cycle Time (min.) @ CL = 3 7.5 7.5 ns
tAC
Clock Access Time (min.) @ CL= 3
5.4
5.4
ns
fCK Clock Frequency (max.) @ CL = 2 133 100 MHz
tCK Clock Cycle Time (min.) @ CL = 2 7.5
10
ns
tAC
Clock Access Time (min.) @ CL= 2
5.4
6
ns
Description
The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 16M × 72, 32M x 72, 64M × 72, 128M × 72 and 256M x 72 high speed memory arrays designed with
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM
and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive
loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors
are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial
E2PROM using the 2-pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint.
INFINEON Technologies
1
2002-07-18
1 Page HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12 Address Inputs (A12 is used for
256Mbit based modules only)
DQMB0 - DQMB7 Data Mask
BA0, BA1
Bank Selects
CS0 - CS3
Chip Select
DQ0 - DQ63 Data Input/Output
REGE*)
Register Enable
“H” or N.C = registered mode
“L” = buffered mode
CB0 - CB7
RAS
CAS
Check Bits
Row Address Strobe
Column Address Strobe
VDD
VSS
SCL
Power (+ 3.3 V)
Ground
Clock for Presence Detect
WE Read/Write Input
SDA
Serial Data Out
CKE0
Clock Enable
N.C.
No Connection
CLK0 - CLK3 Clock Input
––
Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
Banks
SDRAMs columns bits
128 MB 16M × 72 1
16M × 4 18
12/2/10
4k 64 ms 15.6 µs
128 MB 16M × 72 1
16M x 8 9
12/2/10
4k 64 ms 15.6 µs
256 MB 32M x 72 1
32M x 4 18
12/2/11
4k 64 ms 15.6 µs
256 MB 32M x 72 1
32M x 8 9
13/2/10
8k 64 ms 7.8 µs
512 MB 64M × 72 1
64M × 4 18
13/2/11
8k 64 ms 7.8 µs
1 GB 128M × 72 2
64M × 4 36
13/2/11
8k 64 ms 7.8 µs
1 GB 128M × 72 1
128M × 4 18
13/2/12
8k 64ms 7.8 µs
2 GB 256M × 72 2
128M × 4 36
13/2/12
8k 64ms 7.8 µs
INFINEON Technologies
3
2002-07-18
3Pages HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
RCS0
RDQMB0
D Q 0 -D Q 7
CS
DQM
DQ 0-DQ 7
D0
RDQMB4
DQ 32-DQ 39
CS
DQM
D Q 0 -D Q 7
D4
RDQMB1
D Q 8 -D Q 1 5
CS
DQM
DQ 0-DQ 7
D1
RDQMB5
DQ 40-DQ 47
CS
DQM
D Q 0 -D Q 7
D5
CB0- CB7
RCS2
RDQMB2
D Q 1 6 -D Q 2 3
CS WE
DQM
DQ 0-DQ 7
D8
CS
DQM
DQ 0-DQ 7
D2
RDQMB4
DQ 48-DQ 55
CS
DQM
D Q 0 -D Q 7
D6
RDQMB3
D Q 2 4 -D Q 3 1
CS
DQM
DQ 0-DQ 7
D3
RDQMB7
DQ 56-DQ 63
CS
DQM
D Q 0 -D Q 7
D7
V
CC
V
SS
C LK 0
12 pF
C S0/C S2
DQM B0-7
BA0, BA1
A0-A11,12* )
RAS
CAS
CKE0
WE
D 0-D 8, R eg., D LL
C
D 0-D 8, R eg., D LL
PLL SDRAM s D0-D8
R C S0/R C S2
RDQM B0-7
RBA0, RBA1
R A0-11,12
RRAS
RCAS
RCKE0
RW E
SDRA M s D0-D8
SDRA M s D0-D8
SDRA M s D0-D8
SDRA M s D0-D8
SDRA M s D0-D8
SDRA M s D0-D8
E 2P RO M
(25 6 w o rd x 8 B it)
SA0 SA0
SA1 SA1 SDA
SA2 SA2 WP
SCL SCL
47 kΩ
N ote s:
1) DQ w irding m ay differ from that
d e crib e d in th is d ra w in g ;
how ever D Q /DQ B relationship
m ust be m aintained as show n
2) A ll res is to rs are 10 Ω un le ss
otherw ise noted
*) A 1 2 is o n ly fo r 32 M x 72
o rg a n is a tio n
REGE
10 kΩ
V
CC
CLK1, CLK2, CLK3
Block Diagram: One Bank 16M x72 and 32M x 72 Modules
HYS72V16301 & HYS72V32300GR using x8 organized SDRAMs
12 pF
SP B 04130-2
INFINEON Technologies
6
2002-07-18
6 Page | |||
ページ | 合計 : 22 ページ | ||
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部品番号 | 部品説明 | メーカ |
HYS72V32300GR-75-C2 | PC133 Registered SDRAM-Modules | Infineon |
HYS72V32300GR-75-D | PC133 Registered SDRAM-Modules | Infineon |