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74LVC10D の電気的特性と機能

74LVC10DのメーカーはPhilipsです、この部品の機能は「Triple 3-input NAND gate」です。


製品の詳細 ( Datasheet PDF )

部品番号 74LVC10D
部品説明 Triple 3-input NAND gate
メーカ Philips
ロゴ Philips ロゴ 




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74LVC10D Datasheet, 74LVC10D PDF,ピン配置, 機能
INTEGRATED CIRCUITS
74LVC10
Triple 3-input NAND gate
Product specification
Replaces data sheet of 1996 Feb
IC24 Data Handbook
Philips
Semiconductors
1997 Apr 28

1 Page





74LVC10D pdf, ピン配列
Philips Semiconductors
Triple 3-input NAND gate
Product specification
74LVC10
LOGIC SYMBOL (IEEE/IEC)
1
2
&
13
3
4
&
5
9
10
&
11
12
6
8
LOGIC DIAGRAM (ONE GATE)
A
B
C
Y
SV00418
FUNCTION TABLE
INPUTS
nA nB
LL
LL
LH
LH
HL
HL
HH
HH
NOTES:
H = HIGH voltage level
L = LOW voltage level
SV00419
OUTPUTS
nC nY
LH
HH
LH
HH
LH
HH
LH
HL
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VCC
VCC
VI
VI/O
VO
Tamb
tr, tf
DC supply voltage (for max. speed performance)
DC supply voltage (for low-voltage applications)
DC input voltage range
DC input voltage range for I/Os
DC output voltage range
Operating free-air temperature range
Input rise and fall times
CONDITIONS
VCC = 1.2 to 2.7V
VCC = 2.7 to 3.6V
LIMITS
MIN MAX
2.7 3.6
1.2 3.6
0 5.5
0 VCC
0 VCC
–40 +85
0 20
0 10
UNIT
V
V
V
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITIONS
RATING
UNIT
VCC DC supply voltage
–0.5 to +6.5
V
IIK DC input diode current
VI t 0
–50 mA
VI DC input voltage
Note 2
–0.5 to +5.5
V
VI/O DC input voltage range for I/Os
–0.5 to VCC +0.5
V
IOK DC output diode current
VO uVCC or VO t 0
"50
mA
VOUT DC output voltage
Note 2
–0.5 to VCC +0.5
V
IOUT
DC output source or sink current
VO = 0 to VCC
"50
mA
IGND, ICC DC VCC or GND current
"100
mA
Tstg Storage temperature range
–60 to +150
°C
PTOT
Power dissipation per package
– plastic mini-pack (SO)
– plastic shrink mini-pack (SSOP and TSSOP)
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
500
500
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1997 Apr 28
3


3Pages


74LVC10D 電子部品, 半導体
Philips Semiconductors
Triple 3-input NAND gate
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
Product specification
74LVC10
SOT337-1
1997 Apr 28
6

6 Page



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共有リンク

Link :


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74LVC10

Triple 3-input NAND gate

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74LVC109

Dual JK flip-flop with set and reset; positive-edge trigger

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74LVC10A

Triple 3-input NAND gate

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74LVC10D

Triple 3-input NAND gate

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