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74LCX162374 の電気的特性と機能

74LCX162374のメーカーはFairchild Semiconductorです、この部品の機能は「Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26 Series Resistors」です。


製品の詳細 ( Datasheet PDF )

部品番号 74LCX162374
部品説明 Low Voltage 16-Bit D-Type Flip-Flop with 5V Tolerant Inputs and Outputs and 26 Series Resistors
メーカ Fairchild Semiconductor
ロゴ Fairchild Semiconductor ロゴ 




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74LCX162374 Datasheet, 74LCX162374 PDF,ピン配置, 機能
February 2001
Revised August 2001
74LCX162374
Low Voltage 16-Bit D-Type Flip-Flop
with 5V Tolerant Inputs and Outputs
and 26Series Resistors
General Description
The LCX162374 contains sixteen non-inverting D-type
flip-flops with 3-STATE outputs and is intended for bus ori-
ented applications. The device is byte controlled. A buff-
ered clock (CP) and Output Enable (OE) are common to
each byte and can be shorted together for full 16-bit opera-
tion.
The LCX162374 is designed for low voltage (2.5V or 3.3V)
VCC applications with capability of interfacing to a 5V signal
environment. The 26series resistor in the output helps
reduce output overshoot and undershoot.
The LCX162374 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing CMOS low power dissipation.
Features
I 5V tolerant inputs and outputs
I 2.3V–3.6V VCC specifications provided
I Equivalent 26series resistor on outputs
I 7.0 ns tPD max (VCC = 3.3V), 20 µA ICC max
I Power down high impedance inputs and outputs
I Supports live insertion/withdrawal (Note 1)
I ±12 mA output drive (VCC = 3.0V)
I Implements patented noise/EMI reduction circuitry
I Latch-up performance exceeds 500 mA
I ESD performance:
Human body model > 2000V
Machine model > 200V
I Also packaged in plastic Fine-Pitch Ball Grid Array
(FBGA) (Preliminary)
Note 1: To ensure the high-impedance state during power up or down, OE
should be tied to VCC through a pull-up resistor: the minimum value or the
resistor is determined by the current-sourcing capability of the driver.
Ordering Code:
Order Number Package Number
Package Description
74LCX162374GX
(Note 2)
BGA54A
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
(Preliminary) [TAPE and REEL]
74LCX162374MEA
(Note 3)
MS48A
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
74LCX162374MTD
(Note 3)
MTD48
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 2: BGA package available in Tape and Reel only.
Note 3: Devices also available in Tape and Reel. Specify by appending the suffix letter Xto the ordering code.
Logic Symbol
© 2001 Fairchild Semiconductor Corporation DS500442
www.fairchildsemi.com

1 Page





74LCX162374 pdf, ピン配列
Functional Description
The LCX162374 consists of sixteen edge-triggered
flip-flops with individual D-type inputs and 3-STATE true
outputs. The device is byte controlled with each byte func-
tioning identically, but independent of the other. The control
pins can be shorted together to obtain full 16-bit operation.
Each byte has a buffered clock and buffered Output Enable
common to all flip-flops within that byte. The description
which follows applies to each byte. Each flip-flop will store
Logic Diagrams
the state of their individual D inputs that meet the setup and
hold time requirements on the LOW-to-HIGH Clock (CPn)
transition. With the Output Enable (OEn) LOW, the con-
tents of the flip-flops are available at the outputs. When
OEn is HIGH, the outputs go to the high impedance state.
Operation of the OEn input does not affect the state of the
flip-flops.
Byte 1 (0:7)
Byte 2 (8:15)
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3 www.fairchildsemi.com


3Pages


74LCX162374 電子部品, 半導体
AC LOADING and WAVEFORMS Generic for LCX Family
FIGURE 1. AC Test Circuit (CL includes probe and jig capacitance)
Test
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
Switch
Open
6V at VCC = 3.3 ± 0.3V, and 2.7V
VCC x 2 at VCC = 2.5 ± 0.2V
GND
Waveform for Inverting and Non-Inverting Functions
3-STATE Output High Enable and
Disable Times for Logic
Propagation Delay. Pulse Width and trec Waveforms
Setup Time, Hold Time and Recovery Time for Logic
3-STATE Output Low Enable and
Disable Times for Logic
trise and tfall
FIGURE 2. Waveforms
(Input Characteristics; f =1MHz, tr = tf = 3ns)
Symbol
Vmi
Vmo
Vx
Vy
3.3V ± 0.3V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
VCC
2.7V
1.5V
1.5V
VOL + 0.3V
VOH 0.3V
2.5V ± 0.2V
VCC/2
VCC/2
VOL + 0.15V
VOH 0.15V
www.fairchildsemi.com
6

6 Page



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共有リンク

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部品番号部品説明メーカ
74LCX162373

Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor

Fairchild Semiconductor
Fairchild Semiconductor
74LCX162373GX

Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor

Fairchild Semiconductor
Fairchild Semiconductor
74LCX162373MEA

Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor

Fairchild Semiconductor
Fairchild Semiconductor
74LCX162373MTD

Low Voltage 16-Bit Transparent Latch with 5V Tolerant Inputs and Outputs and 26 Series Resistor

Fairchild Semiconductor
Fairchild Semiconductor


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