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74HCT166 の電気的特性と機能

74HCT166のメーカーはPhilipsです、この部品の機能は「8-bit parallel-in/serial-out shift register」です。


製品の詳細 ( Datasheet PDF )

部品番号 74HCT166
部品説明 8-bit parallel-in/serial-out shift register
メーカ Philips
ロゴ Philips ロゴ 




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74HCT166 Datasheet, 74HCT166 PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT166
8-bit parallel-in/serial-out shift
register
Product specification
File under Integrated Circuits, IC06
December 1990

1 Page





74HCT166 pdf, ピン配列
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT166
PIN DESCRIPTION
PIN NO.
1
2, 3, 4, 5, 10, 11, 12, 14
6
7
8
9
13
15
16
SYMBOL
Ds
D0 to D7
CE
CP
GND
MR
Q7
PE
VCC
NAME AND FUNCTION
serial data input
parallel data inputs
clock enable input (active LOW)
clock input (LOW-to-HIGH edge-triggered)
ground (0 V)
asynchronous master reset (active LOW)
serial output from the last stage
parallel enable input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3


3Pages


74HCT166 電子部品, 半導体
Philips Semiconductors
8-bit parallel-in/serial-out shift register
Product specification
74HC/HCT166
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
Tamb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25
40 to +85
UNIT
40 to +125
VCC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
tPHL/ tPLH propagation delay
CP to Q7
tPHL propagation delay
MR to Q7
50 150 190 225 ns 2.0 Fig.7
18 30 38 45 4.5
14 26 33 38 6.0
47 160 200 240 ns 2.0 Fig.8
17 32 40 48 4.5
14 27 34 41 6.0
tTHL/ tTLH output transition time
19 75 95 110 ns 2.0 Fig.7
7 15 19 22 4.5
6 13 16 19 6.0
tW clock pulse width 80 17
HIGH or LOW
16 6
14 5
100 120 ns 2.0 Fig.7
20 24
4.5
17 20
6.0
tW master reset pulse width 100 25
LOW
20 9
17 7
125 150 ns 2.0 Fig.8
25 30
4.5
21 26
6.0
trem removal time
MR to CP
0 19
0
0
ns 2.0 Fig.8
0 7
0
0
4.5
0 6
0
0
6.0
tsu set-up time
Dn, CE to CP
80 14
16 5
14 4
100 120 ns 2.0 Fig.9
20 24
4.5
17 20
6.0
tsu set-up time
PE to CP
100 33
20 12
17 10
125 150 ns 2.0 Fig.8
25 30
4.5
21 26
6.0
th hold time
2 8
2
2
ns 2.0 Fig.8
Dn, CE to CP
2 3
2
2
4.5
2 2
2
2
6.0
th hold time
PE to CP
0 28
0
0
ns 2.0 Fig.9
0 10
0
0
4.5
0 8
0
0
6.0
fmax maximum clock pulse 6.0 19 4.8 4.0 MHz 2.0 Fig.7
frequency
30 57 24 20
4.5
35 68 28 24
6.0
December 1990
6

6 Page



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共有リンク

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