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X1205 の電気的特性と機能

X1205のメーカーはXicorです、この部品の機能は「Real Time Clock/Calendar」です。


製品の詳細 ( Datasheet PDF )

部品番号 X1205
部品説明 Real Time Clock/Calendar
メーカ Xicor
ロゴ Xicor ロゴ 




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X1205 Datasheet, X1205 PDF,ピン配置, 機能
Preliminary Information
New Features
Repetitive Alarms &
Temperature Compensation
X1205
Real Time Clock/Calendar
2-WireRTC
FEATURES
• Real Time Clock/Calendar
—Tracks time in Hours, Minutes, and Seconds
—Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
—Settable on the Second, Minute, Hour, Day of
the Week, Day, or Month
—Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
—Internal feedback resistor and compensation
capacitors
—64 position Digitally Controlled Trim Capacitor
—6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 2-Wire™ Interface interoperable with I2C*
—400kHz data transfer rate
• Low Power CMOS
—1.25µA Operating Current (Typical)
• Small Package Options
—8-Lead SOIC and 8-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
DESCRIPTION
The X1205 device is a Real Time Clock with clock/
calendar, two polled alarms, oscillator compensation,
and battery backup switch.
The oscillator uses an external, low-cost 32.768kHz
crystal. All compensation and trim components are
integrated on the chip. This eliminates several external
discrete components and a trim capacitor, saving
board area and component cost.
The Real-Time Clock keeps track of time with separate
registers for Hours, Minutes, and Seconds. The
Calendar has separate registers for Date, Month, Year
and Day-of-week. The calendar is correct through
2099, with automatic leap year correction.
BLOCK DIAGRAM
OSC
Compensation
32.768kHz
X1
X2
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Time
Keeping
Registers
(SRAM)
SCL
SDA
Serial
Interface
Decoder
IRQ
Control
Decode
Logic
8
*I2C is a Trademark of Philips.
REV 1.0.9 8/29/02
Control
Registers
(EEPROM)
Status
Registers
(SRAM)
Interrupt Enable
Alarm
www.xicor.com
Alarm
Compare
Alarm Regs
(EEPROM)
Characteristics subject to change without notice. 1 of 22

1 Page





X1205 pdf, ピン配列
X1205 – Preliminary Information
the course of a read operation. In this device, the time is
latched by the read command (falling edge of the clock
on the ACK bit prior to RTC data output) into a separate
latch to avoid time changes during the read operation.
The clock continues to run. Alarms occurring during a
read are unaffected by the read operation.
Writing to the Real Time Clock
The time and date may be set by writing to the RTC
registers. To avoid changing the current time by an
uncompleted write operation, the current time value is
loaded into a separate buffer at the falling edge of the
clock on the ACK bit before the RTC data input bytes,
the clock continues to run. The new serial input data
replaces the values in the buffer. This new RTC value
is loaded back into the RTC Register by a stop bit at
the end of a valid write sequence. An invalid write
operation aborts the time update procedure and the
contents of the buffer are discarded. After a valid write
operation the RTC will reflect the newly loaded data
beginning with the next “one second clock cycle” after
the stop bit is written. The RTC continues to update
the time while an RTC register write is in progress and
the RTC continues to run during any nonvolatile write
sequences. A single byte may be written to the RTC
without affecting the other bytes.
Accuracy of the Real Time Clock
The accuracy of the Real Time Clock depends on the
frequency of the quartz crystal that is used as the time
base for the RTC. Since the resonant frequency of a
crystal is temperature dependent, the RTC perfor-
mance will also be dependent upon temperature. The
frequency deviation of the crystal is a function of the
turnover temperature of the crystal from the crystal’s
nominal frequency. For example, a >20ppm frequency
deviation translates into an accuracy of >1 minute per
month. These parameters are available from the
crystal manufacturer. Xicor’s RTC family provides on-
chip crystal compensation networks to adjust load-
capacitance to tune oscillator frequency from +116
ppm to –37 ppm when using a 12.5 pF load crystal.
For more detail information see the Application
section.
CLOCK/CONTROL REGISTERS (CCR)
The Control/Clock Registers are located in an area
accessible following a slave byte of “1101111x” and
reads or writes to addresses [0000h:003Fh]. The
clock/control memory map has memory addresses
from 0000h to 003Fh. The defined addresses are
described in the Table 1. Writing to and reading from
the undefined addresses are not recommended.
CCR access
The contents of the CCR can be modified by perform-
ing a byte or a page write operation directly to any
address in the CCR. Prior to writing to the CCR
(except the status register), however, the WEL and
RWEL bits must be set using a two step process (See
section “Writing to the Clock/Control Registers.”)
The CCR is divided into 5 sections. These are:
1. Alarm 0 (8 bytes; non-volatile)
2. Alarm 1 (8 bytes; non-volatile)
3. Control (4 bytes; non-volatile)
4. Real Time Clock (8 bytes; volatile)
5. Status (1 byte; volatile)
Each register is read and written through buffers. The
non-volatile portion (or the counter portion of the RTC) is
updated only if RWEL is set and only after a valid write
operation and stop bit. A sequential read or page write
operation provides access to the contents of only one
section of the CCR per operation. Access to another sec-
tion requires a new operation. Continued reads or writes,
once reaching the end of a section, will wrap around to
the start of the section. A read or write can begin at any
address in the CCR.
It is not necessary to set the RWEL bit prior to writing
the status register. Section 5 supports a single byte
read or write only. Continued reads or writes from this
section terminates the operation.
The state of the CCR can be read by performing a ran-
dom read at any address in the CCR at any time. This
returns the contents of that register location. Addi-
tional registers are read by performing a sequential
read. The read instruction latches all Clock registers
into a buffer, so an update of the clock does not
change the time being read. A sequential read of the
CCR will not result in the output of data from the mem-
ory array. At the end of a read, the master supplies a
stop condition to end the operation and free the bus.
After a read of the CCR, the address remains at the
previous address +1 so the user can execute a current
address read of the CCR and continue reading the
next Register.
ALARM REGISTERS
There are two alarm registers whose contents mimic the
contents of the RTC register, but add enable bits and
exclude the 24 hour time selection bit. The enable bits
specify which registers to use in the comparison between
the Alarm and Real Time Registers. For example:
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice. 3 of 22


3Pages


X1205 電子部品, 半導体
X1205 – Preliminary Information
INTERRUPT CONTROL REGISTER (INT)
Interrupt Control and Status Bits (IM, AL1E, AL0E)
There are two Interrupt Control bits, Alarm 1 Interrupt
Enable (AL1E) and Alarm 0 Interrupt Enable (AL0E) to
specifically enable or disable the alarm interrupt signal
output (IRQ). The interrupts are enabled when either the
AL1E and AL0E bits are set to “1”, respectively.
Two volatile bits (AL1 and AL0), associated with the two
alarms respectively, indicate if an alarm has happened.
These bits are set on an alarm condition regardless of
whether the IRQ interrupt is enabled. The AL1 and AL0
bits in the status register are reset by the falling edge of
the eighth clock of a read of the register containing the
bits.
Pulse Interrupt Mode
The pulsed interrupt mode allows for repetitive or
recurring alarm functionality. Hence an repetitive or
recurring alarm can be set for every nth second, or nth
minute, or nth hour, or nth date, or for the same day of
the week. The pulsed interrupt mode can be consid-
ered a repetitive interrupt mode, with the repetition
rate set by the time setting fo the alarm.
The Pulse Interrupt Mode is enabled when the IM bit is
set.
IM Bit
0
1
Interrupt / Alarm Frequency
Single Time Event Set By Alarm
Repetitive / Recurring Time Event Set By Alarm
The Alarm IRQ output will output a single pulse of
short duration (approximately 10-40ms) once the
alarm condition is met. If the interrupt mode bit (IM bit)
is set, then this pulse will be periodic.
ON-CHIP OSCILLATOR COMPENSATION
Digital Trimming Register (DTR) — DTR2, DTR1
and DTR0 (Non-Volatile)
The digital trimming Bits DTR2, DTR1 and DTR0
adjust the number of counts per second and average
the ppm error to achieve better accuracy.
DTR2 is a sign bit. DTR2=0 means frequency
compensation is > 0. DTR2=1 means frequency
compensation is < 0.
DTR1 and DTR0 are scale bits. DTR1 gives 10 ppm
adjustment and DTR0 gives 20 ppm adjustment.
A range from -30ppm to +30ppm can be represented
by using three bits above.
Table 3. Digital Trimming Registers
DTR Register
Estimated frequency
DTR2 DTR1 DTR0
PPM
000
0 (default)
010
001
+10
+20
011
+30
100
110
0
-10
101
-20
111
-30
Analog Trimming Register (ATR) (Non-volatile)
Six analog trimming Bits from ATR5 to ATR0 are pro-
vided to adjust the on-chip loading capacitance range.
The on-chip load capacitance ranges from 3.25pF to
18.75pF. Each bit has a different weight for capaci-
tance adjustment. In addition, using a Citizen CFS-206
crystal with different ATR bit combinations provides an
estimated ppm range from +116ppm to -37ppm to the
nominal frequency compensation. The combination of
digital and analog trimming can give up to +146ppm
adjustment.
The on-chip capacitance can be calculated as follows:
CATR = [(ATR value, decimal) x 0.25pF] + 11.0pF
Note that the ATR values are in two’s complement,
with ATR(000000) = 11.0pF, so the entire range runs
from 3.25pF to 18.75pF in 0.25pF steps.
The values calculated above are typical, and total load
capacitance seen by the crystal will include approxi-
mately 2pF of package and board capacitance in addi-
tion to the ATR value.
See Application section and Xicor’s Application Note
AN154 for more information.
REV 1.0.9 8/29/02
www.xicor.com
Characteristics subject to change without notice. 6 of 22

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共有リンク

Link :


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