Total 22 pages
8-BIT MTP MICROCONTROLLER
The W78LE52 is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78LE52 is fully compatible with the standard 8051.
The W78LE52 contains an 8K bytes MTP ROM (Multiple-Time Programmable ROM); a 256 bytes
RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; three 16-
bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported by
eight sources two-level interrupt capability. To facilitate programming and verification, the MTP-ROM
inside the W78LE52 allows the program memory to be programmed and read electronically. Once the
code is confirmed, the user can protect the code for security.
The W78LE52 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
• Fully static design 8-bit CMOS microcontroller
• Wide supply voltage of 2.4V to 5.5V
• 256 bytes of on-chip scratchpad RAM
• 8 KB electrically erasable/programmable MTP-ROM
• 64 KB program memory address space
• 64 KB data memory address space
• Four 8-bit bi-directional ports
• One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
• Three 16-bit timer/counters
• One full duplex serial port(UART)
• Watchdog Timer
• Eight sources, two-level interrupt capability
• EMI reduction mode
• Built-in power management
• Code protection mechanism
− DIP 40: W78LE52-24
− PLCC 44: W78LE52P-24
− PQFP 44: W78LE52F-24
Publication Release Date: January 1999
- 1 - Revision A1
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running resets
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) :External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are
alternative function pins. It can be used as general I/O port or external interrupt input
sources (INT2 / INT3 ).
Publication Release Date: January 1999
- 3 - Revision A1
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
P4, #0AH ; Output data "A" through P4.0−P4.3.
; Read P4 status to Accumulator.
; Set bit P4.0
; Clear bit P4.1
3. Reduce EMI Emission
Because of on-chip MTP-ROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space. The
AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from
oscillation circuitry, W78LE52 allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 24MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
- - - - - - - AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
POF GF1 GF0
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.