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W78LE51 の電気的特性と機能

W78LE51のメーカーはWinbondです、この部品の機能は「8-BIT MTP MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 W78LE51
部品説明 8-BIT MTP MICROCONTROLLER
メーカ Winbond
ロゴ Winbond ロゴ 




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W78LE51 Datasheet, W78LE51 PDF,ピン配置, 機能
Preliminary W78LE51
8-BIT MTP MICROCONTROLLER
GENERAL DESCRIPTION
The W78LE51 is an 8-bit microcontroller which can accommodate a wide supply voltage range with
low power consumption. The instruction set for the W78LE51 is fully compatible with the standard
8051. The W78LE51 contains an 4K bytes MTP ROM (Multiple-Time Programmable ROM); a 128
bytes RAM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit I/O port P4; two
16-bit timer/counters; a hardware watchdog timer and a serial port. These peripherals are supported
by seven sources two-level interrupt capability. To facilitate programming and verification, the MTP-
ROM inside the W78LE51 allows the program memory to be programmed and read electronically.
Once the code is confirmed, the user can protect the code for security.
The W78LE51 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 2.4V to 5.5V
128 bytes of on-chip scratchpad RAM
4 KB electrically erasable/programmable MTP-ROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC/QFP package)
Two 16-bit timer/counters
One full duplex serial port(UART)
Watchdog Timer
seven sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
DIP 40: W78LE51-24
PLCC 44: W78LE51P-24
PQFP 44: W78LE51F-24
Publication Release Date: December 1998
- 1 - Revision A1

1 Page





W78LE51 pdf, ピン配列
Preliminary W78LE51
PIN DESCRIPTION
SYMBOL
EA
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PSEN
ALE
RST
XTAL1
XTAL2
VSS
VDD
P0.0P0.7
P1.0P1.7
P2.0P2.7
P3.0P3.7
P4.0P4.3
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The pins of Port 0 can be
individually configured to open-drain or standard port with internal pull-ups.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2) : External Interrupt 0
INT1(P3.3) : External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR (P3.6) :External Data Memory Write Strobe
RD (P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are
alternative function pins. It can be used as general I/O port or external interrupt input
sources (INT2 / INT3 ).
Publication Release Date: December 1998
- 3 - Revision A1


3Pages


W78LE51 電子部品, 半導体
Preliminary W78LE51
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR,
which is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses
external ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off
again after it has been completely accessed or the program returns to internal ROM code space. The
AO bit in the AUXR register, when set, disables the ALE output. In order to reduce EMI emission from
oscillation circuitry, W78LE51 allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may effect to external crystal operating improperly at high frequency above 24 MHz. The
value of R and C1,C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
- - - - - - - AO
AO: Turn off ALE output.
4. Power-off Flag
***PCON - Power control (87H)
-
-
-
POF GF1 GF0
PD
IDL
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD: Power down mode bit. Set it to enter power down mode.
IDL: Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide
the system clock. The divider output is selectable and determines the time-out interval. When the
time-out occurs a system reset can also be caused if it is enabled. The main use of the Watchdog
timer is as a system monitor. This is important in real-time control applications. In case of power
glitches or electro-magnetic interference, the processor may begin to execute errant code. If this is
left unchecked the entire system may crash. The watchdog time-out selection will result in different
time-out values depending on the clock speed. The Watchdog timer will de disabled on reset. In
general, software should restart the Watchdog timer to put it into a known state. The control bits that
support the Watchdog timer are discussed below.
Watchdog Timer Control Register
Bit: 7 6 5
ENW CLRW WIDL
4
-
3210
- PS2 PS1 PS0
Mnemonic: WDTC
Address: 8FH
ENW : Enable watch-dog if set.
-6-

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
W78LE51

8-BIT MTP MICROCONTROLLER

Winbond
Winbond
W78LE51

8-BIT MICROCONTROLLER

Winbond
Winbond
W78LE51-24

8-BIT MTP MICROCONTROLLER

Winbond
Winbond
W78LE516

8-BIT MICROCONTROLLER

Winbond
Winbond


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