W78L801P-24 データシート ( 8-BIT MICROCONTROLLER )

部品番号

W78L801P-24

部品説明

8-BIT MICROCONTROLLER

メーカ

Winbond

ロゴ

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W78L801

8-BIT MICROCONTROLLER

GENERAL DESCRIPTION

The W78L801 is an 8-bit microcontroller which can accommodate a wide range of supply voltages

with low power consumption. The instruction set for the W78L801 is fully compatible with the standard

8051. The W78L801 contains an 4K bytes Mask ROM; a 256 bytes RAM; four 8-bit bi-directional and

bit-addressable I/O ports; an additional 6-bit I/O port P4; two 16-bit timer/counters; a hardware

watchdog timer. These peripherals are supported by a twelve sources two-level interrupt capability.

The W78L801 does not contain serial port.

The W78L801 microcontroller has two power reduction modes, idle mode and power-down mode,

both of which are software selectable. The idle mode turns off the processor clock but allows for

continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power

consumption. The external clock can be stopped at any time and in any state without affecting the

processor.

FEATURES

• Fully static design 8-bit CMOS microcontroller

• Wide supply voltage of 1.8V to 5.5V

• DC-24 MHz operation

• 256 bytes of on-chip scratchpad RAM

• 4 KB Mask-ROM

• 64 KB program memory address space

• 64 KB data memory address space

• Four 8-bit bi-directional ports

• Two 16-bit timer/counters

• Watchdog Timer

• Direct LED drive outputs

• Twelve sources, two-level interrupt capability

• Wake-up via external interrupts at Port 1

• EMI reduction mode

• Built-in power management

• Code protection mechanism

• Packages:

− DIP 40: W78L801-24

− PLCC 44: W78L801P-24

− PQFP 44: W78L801F-24

Publication Release Date: February 1999

- 1 - Revision A3

1 Page

W78L801

PIN DESCRIPTION

SYMBOL

DESCRIPTIONS

EA EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of

external ROM. It should be kept high to access internal ROM. The ROM address and

data will not be presented on the bus if EA pin is high and the program counter is

within on-chip ROM area. Otherwise they will be presented on the bus.

PSEN

PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0

address/ data bus during fetch and MOVC operations. When internal ROM access is

performed, no PSEN strobe signal outputs from this pin. This pin also serves the

alternative function P4.6.

ALE ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates

the address from the data on Port 0. This pin also serves the alternative function P4.5

RST

RESET: A high on this pin for two machine cycles while the oscillator is running resets

the device.

XTAL1 CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external

clock.

XTAL2 CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.

VSS GROUND: Ground potential

VDD POWER SUPPLY: Supply voltage for operation.

P0.0−P0.7 PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order

address/data bus during accesses to external memory. The pins of Port 0 can be

individually configured to open-drain or standard port with internal pull-ups.

P1.0−P1.7 PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate

functions which are described below:

INT2−INT9(P1.0−P1.7): External interrupt 2 to 9

P2.0−P2.7 PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides

the upper address bits for accesses to external memory.

P3.0−P3.7 PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. The pins P3.4 to P3.7

can be configured with high sink current which can drive LED displays directly. All bits

have alternate functions, which are described below:

INT0 (P3.2) : External Interrupt 0

INT1(P3.3) : External Interrupt 1

T0(P3.4) : Timer 0 External Input

T1(P3.5) : Timer 1 External Input

WR (P3.6) : External Data Memory Write Strobe

RD (P3.7) : External Data Memory Read Strobe

P4.0−P4.6 PORT 4: A 6-bit bi-directional I/O port which is bit-addressable. Pins P4.0 to P4.3 are

available on 44-pin PLCC/QFP package. Pins P4.5 and P4.6 are the alternative

function corresponding to ALE and PSEN.

Publication Release Date: February 1999

- 3 - Revision A3

3Pages

W78L801

1 interrupts. Each flag in IRQ register will be set when an interrupt request is recognized but must be

cleared by software. Note that the interrupt flags have to be cleared before the interrupt service

routine is completed, or else another interrupt will be generated.

Interrupt Enable Register 0

Bit: 7

EA -

Mnemonic: IE

43210

- ET1 EX1 ET0 EX0

Address: A8H

EA : Global enable. Enable/disable all interrupts.

ET1: Enable Timer 1 interrupt

EX1: Enable external interrupt 1

ET0: Enable Timer 0 interrupt

EX0: Enable external interrupt 0

Interrupt Enable Register 1

Bit: 7 6 5 4 3 2 1 0

EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2

Mnemonic: IE1

Address: E8H

EX9: Enable external interrupt 9

EX8: Enable external interrupt 8

EX7: Enable external interrupt 7

EX6: Enable external interrupt 6

EX5: Enable external interrupt 5

EX4: Enable external interrupt 4

EX3: Enable external interrupt 3

EX2: Enable external interrupt 2

Note: 0 = interrupt disabled, 1 = interrupt enabled.

Interrupt Priority Register 0

Bit: 7 6 5 4 3 2 1 0

- PS1 PT2 PS PT1 PX1 PT0 PX0

Mnemonic: IP0

Address: B8h

IP.7: Unused.

PS1: This bit defines the Serial port 1 interrupt priority. PS = 1 sets it to higher priority level.

PT2: This bit defines the Timer 2 interrupt priority. PT2 = 1 sets it to higher priority level.

PS : This bit defines the Serial port 0 interrupt priority. PS = 1 sets it to higher priority level.

PT1: This bit defines the Timer 1 interrupt priority. PT1 = 1 sets it to higher priority level.

PX1: This bit defines the External interrupt 1 priority. PX1 = 1 sets it to higher priority level.

PT0: This bit defines the Timer 0 interrupt priority. PT0 = 1 sets it to higher priority level.

PX0: This bit defines the External interrupt 0 priority. PX0 = 1 sets it to higher priority level.

-6-

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