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PDF W78L51 Data sheet ( 特性 )

部品番号 W78L51
部品説明 8-BIT MICROCONTROLLER
メーカ Winbond
ロゴ Winbond ロゴ 

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W78L51 Datasheet, W78L51 PDF,ピン配置, 機能
W78L51
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78L51 microcontroller supplies a wider frequency and supply voltage range than most 8-bit
microcontrollers on the market. It is compatible with the industry standard 80C51 microcontroller
series.
The W78L51 contains four 8-bit bidirectional parallel ports, one extra 4-bit bit-addressable I/O port
(Port 4) and two additional external interrupts (INT2 , INT3 ), two 16-bit timer/counters, one watchdog
timer and a serial port. These peripherals are supported by a seven-source, two-level interrupt
capability. There are 128 bytes of RAM and an 4K byte mask ROM for application programs.
The W78L51 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design
Supply voltage of 1.8V to 5.5V
DC-24 MHz operation
128 bytes of on-chip scratchpad RAM
4K bytes of on-chip mask ROM
64K bytes program memory address space
64K bytes data memory address space
Four 8-bit bidirectional ports
Two 16-bit timer/counters
One full duplex serial port
Seven-source, two-level interrupt capability
One extra 4-bit bit-addressable I/O port
Two additional external interrupts INT2 / INT3
Watchdog timer
EMI reduction mode
Built-in power management
Code protection
Packages:
DIP 40: W78L51-24
PLCC 44: W78L51P-24
QFP 44: W78L51F-24
Publication Release Date: January 1999
- 1 - Revision A2

1 Page





W78L51 pdf, ピン配列
W78L51
PIN DESCRIPTION
P0.0P0.7
Port 0, Bits 0 through 7. Port 0 is a bidirectional I/O port. This port also provides a multiplexed low
order address/data bus during accesses to external memory.
P1.0P1.7
Port 1, Bits 0 through 7. Port 1 is a bidirectional I/O port with internal pull-ups.
P2.0P2.7
Port 2, Bits 0 through 7. Port 2 is a bidirectional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
P3.0P3.7
Port 3, Bits 0 through 7. Port 3 is a bidirectional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
PIN
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
ALTERNATE FUNCTION
RXD Serial Receive Data
TXD Serial Transmit Data
INT0 External Interrupt 0
INT1 External Interrupt 1
T0 Timer 0 Input
T1 Timer 1 Input
WR Data Write Strobe
RD Data Read Strobe
P4.0P4.3
Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative function pins. It can
be used as general I/O pins or external interrupt input sources (INT2 / INT3 ).
EA
External Address Input, active low. This pin forces the processor to execute out of external ROM.
This pin should be kept low for all W78C31 operations.
RST
Reset Input, active high. This pin resets the processor. It must be kept high for at least two machine
cycles in order to be recognized by the processor.
Publication Release Date: January 1999
- 3 - Revision A2


3Pages


W78L51 電子部品, 半導体
W78L51
New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupts
INT2 , INT3 have been added to either the PLCC or QFP package. And description follows:
1. INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register
is bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
***XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
Seven-source interrupt informations:
INTERRUPT
SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
External Interrupt 2
External Interrupt 3
VECTOR
ADDRESS
03H
0BH
13H
1BH
23H
33H
3BH
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
0 (highest)
IE.0
1 IE.1
2 IE.2
3 IE.3
4 IE.4
5 XICON.2
6 (lowest)
XICON.6
INTERRUPT
TYPE
EDGE/LEVEL
TCON.0
-
TCON.2
-
-
XICON.0
XICON.3
-6-

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