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UPD70325GJ-10-5BG の電気的特性と機能

UPD70325GJ-10-5BGのメーカーはNECです、この部品の機能は「V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 UPD70325GJ-10-5BG
部品説明 V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER
メーカ NEC
ロゴ NEC ロゴ 




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UPD70325GJ-10-5BG Datasheet, UPD70325GJ-10-5BG PDF,ピン配置, 機能
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD70325
V25+TM
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD70325 (V25+) is a single-chip microcontroller on which 16-bit CPU, RAM, serial interface, timer, DMA
controller, interrupt controller, etc. are all integrated. The µPD70325 is software compatible with the 16/8-bit single-
chip microcontroller µPD70320 (V25TM). The V25+ greatly improves the DMA responsivity and transfer rate compared
to the V25.
FEATURES
Software compatible with V25
Software compatible with µPD70108/70116 (in native mode) (some instructions added)
Internal 16-bit architecture and external 8-bit data bus
3-stage pipeline method
Minimum instruction cycle : 250 ns/8 MHz (external 16 MHz)
: 200 ns/10 MHz (external 20 MHz)
Memory space 1 Mbyte
On-chip RAM : 256 words × 8 bits
Register bank (memory mapped method) : 8 banks
Input port (port T) with comparator : 8 bits
I/O lines (input port : 4 bits, input/output ports : 20 bits)
Serial interface : 2 channels
• Internal dedicated baud rate generator
• Asynchronous mode and I/O interface mode
Interrupt controller
• Programmable priority (8 levels)
• 3 types of interrupt response method
Vectored interrupt function, register bank switching function, macro service function
DRAM and pseudo SRAM refreshing function
DMA controller : 2 channels
• 4 types of DMA transfer mode
• Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release
mode)
Maximum 2 Mbytes/second (when stop control is executed by DMARQ pin in demand release
mode, or burst mode)
• Address pointer (linear) : 20 bits
• Terminal counter : 16 bits
16-bit timer : 2 channels
Time base counter (20 bits) : 1 channel
On-chip clock generator
Programmable wait function
Standby function (STOP, HALT)
The information in this document is subject to change without notice.
Document No. U12850EJ7V0DS00 (7th edition)
Date Published November 1997 N
Printed in Japan
The mark shows major revised points.
© 11999965

1 Page





UPD70325GJ-10-5BG pdf, ピン配列
µPD70325
Comparison between V25 and V25+
V25
V35TM
V25+
V35+TM
µPD70320
µPD70330
µPD70325
µPD70335
Transfer processing method
Depends on microprogram
Depends on dedicated hardware
Maximum transfer rate (8-MHz
operation)
0.6 Mbytes/second 0.8 Mbytes/second 4 Mbytes/second 5.3 Mbytes/second
Sampling timing of DMA request
Between instruction execution cycles Between bus cycles
DMA service channel
In on-chip RAM area
In special function register
Specification method of transfer address Segment method
Linear method
Execution format in single-step mode 1 DMA transfer/1 instruction execution
DMA Interrupt request during DMA transfer Accepts only NMI
function (demand release mode)
1 DMA transfer/1 bus cycle
Not accepted
Number of necessary waits when
stop is controlled by DMARQ
(demand release mode)
Not necessary
2 waits
Transfer processing units
Byte/word
Byte/word
Byte
Byte/word
TC (terminal counter) setting value Number of times of DMA transfer
(Number of times of DMA transfer) – 1
Generation timing of terminal counter TC = 0
TC = FFFFH
TC output low-level width
Fixed
Expanded by wait insertion
Transmit clock output in
asynchronous mode (channel 0)
Not available
Available (SCK0 pin)
Serial Serial error register
interface Receive buffer full flag
Yes
No
Serial status register
In serial status register
Transmit buffer empty flag
No
In serial status register
All sent flag
Interrupt
function
Interrupt source register
External data bus
No
No
8 bits
16 bits
In serial status register
Yes
8 bits
16 bits
Maximum operating frequency
8 MHz
10 MHz
3


3Pages


UPD70325GJ-10-5BG 電子部品, 半導体
P20/DMARQ0
P21/DMAAK0
P22/TC0
P23/DMARQ1
P24/DMAAK1
P25/TC1
TxD0
RxD0
P16/SCK0
CTS0
TxD1
RxD1
CTS1
NMI (P10)
P11/INTP0
P12/INTP1
P13/INTP2/INTAK
P14/INT/POLL
PROGRAMMABLE
DMA
CONTROLLER
SERIAL
INTERFACE
BAUD RATE
GENERATOR
PROGRAMMABLE
INTERRUPT
CONTROLLER
LC
etc.
PSW
PC
ALU
TA
TB
TC
INTERNAL RAM
256 byte
• GR
• MACRO SERVICE
CHANNEL
INSTRUCTION DECODER
MICRO SEQUENSER
MICRO ROM
PFP INC
Note
INTERNAL ROM
8 Kbyte
(reserved)
QUEUE
(6 byte)
16-BIT TIMER
TIME BASE
COUNTER
PORT
PORT with
COMPARATOR
TOUT/P15
REFRQ CLKOUT/P07
P0 P1 P2
PT0 to 7 VTH
Note The internal ROM of 8 Kbytes is reserved for specific use such as testing and not user-accessible.
CG
A0 to A19
RESET
HLDAK/P26
HLDRQ/P27
READY/P17
MREQ
MSTB
R/W
IOSTB
POLL/INT/P14
EA
D0 to D7
X1
X2
VDD
GND

6 Page



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共有リンク

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部品番号部品説明メーカ
UPD70325GJ-10-5BG

V25+TM 16/8-BIT SINGLE-CHIP MICROCONTROLLER

NEC
NEC


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